AI Hardware Engineering Intern

Intel Corporation•Santa Clara, CA

1d•$100,598 - $100,602•Hybrid

About The Position

Intel is seeking a PhD student in a relevant technical discipline for an AI Hardware Engineering internship focused on AI inference and infrastructure through hardware/software co-design. The intern will study how model architecture, inference behavior, memory movement, data-center constraints, and software stacks affect customer outcomes such as throughput, latency, time-to-first-token, tokens per second, power consumption, utilization, total cost of ownership, and deployability. The role involves hands-on research and analysis in collaboration with technical researchers and engineers addressing AI hardware and infrastructure challenges. The intern will research next-generation AI infrastructure and analyze GenAI and agentic AI workloads, including inference pipelines and the different requirements of prefill and decode. The work may span chip and system architecture, memory and interconnects, silicon lifecycle execution, software stacks, deployment, benchmarking, and customer requirements. The intern will develop technical recommendations and models, simulations, prototypes, or analysis tools, investigate bottlenecks, and communicate findings through technical and executive-ready materials.

Requirements

Currently pursuing a PhD in Computer Science, Computer Engineering, Electrical Engineering, AI/ML, Systems Engineering, or a related technical discipline.
Strong foundation in computer architecture, operating systems, distributed systems, parallel computing, AI/ML systems, high-performance computing, or systems software.
Familiarity with generative AI models and inference concepts, including transformers, attention, token generation, model serving, quantization, batching, KV cache, long-context workloads, and latency-throughput trade-offs.
Programming experience in one or more of C, C++, Rust, CUDA, SYCL, OpenCL, or a comparable low-level or performance-oriented language.
Cumulative GPA of 3.0 or higher.
Expertise in modern high-performance CPU, GPU, or AI accelerator architecture and hardware/software interactions.
Good understanding of firmware codebases, compilers, kernels, serving stacks, and model architectures.
Understanding of silicon design for subsystems and/or top-level functions with ASICs and SoCs, from architecture specification through production silicon, including memory subsystems and interconnects.

Nice To Haves

Coursework, research, or project experience in computer architecture, VLSI, digital design, ASIC/FPGA systems, compilers, kernel development, GPU programming, distributed systems, high-performance computing, or AI systems.
Experience using profiling, tracing, or benchmarking tools to evaluate CPU, GPU, accelerator, network, memory, storage, or software performance.
Familiarity with AI hardware platforms such as Intel Xeon processors, Intel GPUs, NVIDIA GPUs, AMD GPUs, TPUs, custom AI accelerators, FPGAs, or domain-specific inference ASICs.
Understanding of memory hierarchies and performance concepts, including cache behavior, DRAM, HBM, memory bandwidth and capacity, latency, data locality, DMA, and data movement.
Experience with inference frameworks or runtimes such as vLLM, SGLang, Hugging Face Transformers, PyTorch, Triton, or Ray.
Familiarity with AI systems infrastructure such as Linux, containers, Kubernetes, distributed storage, RDMA over Ethernet, InfiniBand, CXL, PCIe, NVMe, UALink/eSUN-based interconnects, silicon photonics, and cluster-management software.
Some experience with simulation, modeling, emulation, RTL, FPGA prototyping, firmware, driver development, or low-level debugging.
Some experience contributing to open-source systems, ML infrastructure, compiler, kernel, framework, or performance-engineering projects.
Understanding of modern AI software layers, including PyTorch, Hugging Face Transformers, vLLM, SGLang, model serving, TensorRT-LLM, Triton, Kubernetes, and Neocloud design efficiencies.

Responsibilities

Conduct technical research on AI infrastructure, including processors, accelerators, memory systems, networking, storage, rack-scale architecture, power delivery, cooling, and cluster management.
Analyze GenAI and agentic AI workloads and their hardware implications, including transformer inference, mixture-of-experts, multimodal models, real-time inference, and distributed serving.
Evaluate AI inference pipeline behavior, including prefill and decode, memory capacity and bandwidth, KV-cache management, compute utilization, interconnect bandwidth, and latency.
Identify product and system gaps affecting Intel's ability to serve AI customers, including hardware, developer tooling, performance libraries, reference architectures, deployment models, observability, and ecosystem enablement.
Support silicon hardware programs through multiple phases of the silicon lifecycle, from concept through silicon execution.
Develop technical recommendations for what Intel should build, optimize, enable, or partner on to meet AI customer requirements.
Benchmark and compare AI hardware and infrastructure approaches across performance, power efficiency, cost, programmability, memory hierarchy, scalability, ecosystem maturity, and workload fit.
Develop technical models, simulations, prototypes, or analysis tools to evaluate hardware/software trade-offs for AI workloads.
Investigate bottlenecks across compute, memory, networking, storage, and software orchestration, and propose ways to improve end-to-end workload performance.
Work with Intel technical teams and external ISVs to gather information on model requirements, inference bottlenecks, deployment challenges, optimization opportunities, and customer priorities.
Engage AI software ecosystem partners, including model providers, inference-engine developers, cloud providers, framework teams, and ISVs, to understand how software stacks interact with hardware.
Present findings through architecture diagrams, benchmark analyses, technical reports, design recommendations, and executive-ready presentations.