Advanced Semiconductor/MEMS Layout & Routing Engineer - 1106

Quantinuum • Brooklyn Park, MN

10d • $115,000 - $145,000

About The Position

Quantinuum is seeking an Advanced Semiconductor/MEMS Layout & Routing Engineer to join an R&D team developing next-generation ion trap technologies. The role translates complex device concepts into manufacturable mask layouts, from initial design through verification and tapeout. The engineer collaborates with design engineers, fabrication scientists, cross-functional partners, external foundries, and mask suppliers to ensure layouts meet technical requirements, established layout practices, and applicable process design kit requirements. The position is available in Brooklyn Park, Minnesota; Albuquerque, New Mexico; or Broomfield, Colorado. Applicants placed in safety-sensitive positions must submit to a pre-employment drug test.

Quantinuum is a quantum computing company with more than 800 employees and operations across the United States, United Kingdom, Germany, Japan, and Singapore. Its platform serves organizations in sectors including pharmaceuticals, material science, financial services, government, and industry, as well as academic and research institutions.

Requirements

• Bachelor’s degree minimum.
• At least 5 years of experience doing IC, MEMS, or PCB layout using advanced EDA tools such as Cadence Virtuoso, Synopsis, or L-Edit.
• At least 2 years of experience with PDKs, layout hierarchy, routing, verification, and tapeout processes.
• Must be a U.S. Person, defined as a U.S. citizen, permanent resident or green card holder, or worker granted asylum or refugee status.
• Candidates must not be a national of the People’s Republic of China or Russia unless also a U.S. citizen, due to U.S. Government national security requirements.

Nice To Haves

• Advanced degree in electrical engineering, computer science, computer engineering, mechanical engineering, physics, or a related area.
• Experience laying out masks for multiple external (non-captive) foundries across multiple technologies, supporting PDK integration and design rule changes.
• Familiarity with SKILL language scripting.
• Experience with photonics component layout, placement, and routing.
• Familiarity with autorouting tools in IC, PCB, or MEMS layout, and interest in leveraging AI capabilities for layout.
• Experience working in a cross-functional R&D team environment.

Responsibilities

• Develop and refine mask layouts for next-generation ion trap devices using Cadence Virtuoso, klayout, scripting, and related layout tools.
• Partner with design engineers and fabrication scientists to resolve layout challenges and support device development through PDK and design rule refinement.
• Work with multiple external foundries to align layouts and tapeout deliverables with applicable PDKs, process requirements, and foundry best practices.
• Work with the layout team, vendors, and foundries to refine workflows and identify opportunities for automation and AI/ML implementation to improve cycle times.

Benefits

• Competitive compensation and the opportunity to work on groundbreaking technology.
• Flexible work arrangements that support work-life balance.
• Employer-subsidized medical, dental, and vision insurance.
• 401(k) retirement savings plan with company match and a student loan repayment benefit.
• Equity opportunities.
• Generous paid time off, sick leave, and 12 paid holidays annually.
• Paid parental leave.
• Employee discount programs.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior