Advanced Semiconductor/MEMS Layout & Routing Engineer - 1106

Quantinuum•US Albuquerque, NM

About The Position

Quantinuum is seeking an Advanced Semiconductor/MEMS Layout & Routing Engineer to join an R&D team developing next-generation ion trap technologies. The role translates complex device concepts into manufacturable mask layouts, from initial design through verification and tapeout. The engineer works with design engineers, fabrication scientists, cross-functional partners, external foundries, and mask suppliers to ensure layouts meet technical requirements, established layout practices, and applicable process design kit requirements. The position is based in Brooklyn Park, Minnesota; Albuquerque, New Mexico; or Broomfield, Colorado. Applicants placed in safety-sensitive positions must submit to a pre-employment drug test. Due to contractual requirements, applicants must be U.S. persons as defined in the posting. Candidates must also meet the stated national-security restrictions regarding People's Republic of China or Russian nationality unless also a U.S. citizen.

Requirements

Bachelor’s degree minimum.
At least 5 years of experience doing IC, MEMS, or PCB layout using advanced EDA tools such as Cadence Virtuoso, Synopsis, or L-Edit.
At least 2 years of experience with PDKs, layout hierarchy, routing, verification, and tapeout processes.
Must be a U.S. person as defined in the posting: a U.S. citizen, permanent resident or green card holder, or a worker granted asylum or refugee status.
Candidates must not be a People's Republic of China national or Russian national unless also a U.S. citizen, due to national security requirements imposed by the U.S. Government.

Nice To Haves

Advanced degree in electrical engineering, computer science, computer engineering, mechanical engineering, physics, or a related area.
Experience laying out masks for multiple external (non-captive) foundries in multiple technologies, supporting PDK integration and design rule changes.
Familiarity with SKILL language scripting.
Photonics component layout, placement, and routing experience.
Familiarity with auto-routing tools in IC, PCB, or MEMS layout and interest in leveraging AI capabilities for layout.
Experience working in a cross-functional R&D team environment.

Responsibilities

Develop and refine mask layouts for next-generation ion trap devices using Cadence Virtuoso, klayout, scripting, and related layout tools.
Partner with design engineers and fabrication scientists to resolve layout challenges and support device development through PDK and design rule refinement.
Work with multiple external foundries to align layouts and tapeout deliverables with applicable PDKs, process requirements, and foundry best practices.
Collaborate with the layout team, vendors, and foundries to refine workflows and identify opportunities for automation and AI/ML implementation to improve cycle times.