Advanced Package Technology, Senior Principal Engineer

Marvell Technology•Austin, TX

About The Position

The Marvell Advanced Packaging R&D team is responsible for package design and technology development to meet the electrical, mechanical, thermal and system requirements for the next generation high performance computing (HPC), Artificial Intelligence (AI) and networking solutions. The group focuses on signal integrity, power integrity, thermal integrity, mechanical integrity, processability, manufacturability, and reliability, involving high speed signaling and complex power delivery networks (PDNs) requiring innovative and custom solutions to meet constantly evolving customer needs. Many of the new designs require multi-chip, multiple component configurations involving, but not limited to, 2.5D and 3D packages, Co-packaged copper or optics and advanced substrates. Marvell has partnered with the world's leading manufacturers to solve our customer’s most challenging designs and integrations with industry-leading packaging technologies.

Requirements

Deep understanding of advanced 2.5D/3D package technology including (a) CoWoS-S/R/L, (b) EMIB, (c) CPO, (d) CPC.
Strong understanding of chip-package interactions and failure mechanism at component and board level, thermal and warpage management.
Ability to manage programs involving cross-functional teams.
Strong interpersonal skills and willingness to learn new things are necessary along with the ability to work with stakeholders in multiple time zones across the globe.
Strong communication, presentation and documentation skills.
Bachelor’s degree in Mechanical Engineering, Material Science, Electrical Engineering or related fields and 10+ years of related professional experience.
OR Master’s degree and/or PhD in Electrical Engineering, mechanical Engineering, Material Science, or related fields with 5+ years of experience.

Nice To Haves

Leadership experience, either as a people manager or technical lead is a strong plus.
Experience in advanced package and substrate technologies with deep understanding of process and materials, component and board level reliability, warpage and thermal management.
Experience in managing substrate and assembly material vendors, substrate manufacturers, OSATs and foundries.
Experience setting roadmaps, not just executing them.
Demonstrated leadership driving cross-company supplier programs.
Prior experience in data center AI accelerators, networking silicon, or custom HPC silicon.
Ability to influence senior stakeholders across architecture, silicon design, system platform engineering, and supply chain
Understanding of component (substrate, interposer, etc.) and package designs.
Knowledge of signal integrity and power integrity.
Board and system level integration.
Experience with silicon disaggregation and reaggregation and memory integration.
Ability to influence suppliers to align their roadmap with company goals.

Responsibilities

Own the packaging technology roadmap for AI XPU, XPU-attach and Switch
Define system-level package architecture including chiplet topology, interposer/substrate scaling, power delivery network strategy, and thermal design envelope.
Architect and evaluate packaging technology choices, including silicon/glass interposers, EMIB/bridge, hybrid bonding, fan-out, and 3D stacking.
Lead co-design efforts across silicon design, floorplanning, PDN modeling, and mechanical/thermal reliability.
Work with stakeholders to define and validate advanced design rule roadmap for interposer, substrates and packages.
Work with vendors to define and validate equipment, process and material roadmap.
Explore technologies beyond what is currently available, make recommendations, and create and protect IP to maximize performance.
Explore technology feasibility and create proof-of-concept samples.
Collaborate with IP, Si design, package design, production and test teams.
Lead package material selection, substrate stack-up definition, mechanical modeling, and reliability analysis.
Partner with silicon design teams to co-optimize die floorplan, bump map, TSV, and RDL requirements.
Support HBM integration strategy (HBM2E / HBM3 / HBM3E) with interposer or bridge-based designs.
Work with OSATs / Foundry partners to evaluate process capability, manufacturability, yield, and cost.
Perform signal and power integrity trade-off analysis in partnership with SI/PI teams.
Drive package qualification and reliability validation to volume readiness