Wafer Fab Yield Process Engineer

Renesas Electronics • Palm Bay, FL

12h • Onsite

About The Position

The Senior Wafer Fab Yield Engineer drives systematic yield improvement across semiconductor wafer fabrication. The role analyzes manufacturing, inline metrology, defect, wafer-level electrical test, and process data to identify yield-loss mechanisms, determine root causes, and lead sustainable corrective actions.

This senior technical role connects fab process performance to device and product yield. It works cross-functionally with Process Engineering, Equipment Engineering, Process Integration, Product/Test Engineering, Failure Analysis, Quality, and Manufacturing to improve yield, reduce variability, and resolve complex manufacturing problems.

The position is 100% onsite in Palm Bay, Florida. Candidates must meet applicable U.S. person requirements for access to ITAR-controlled articles or technical data. The role supports new-product or technology introduction and manufacturing ramps, and includes mentoring less-experienced engineers. Renesas describes itself as an embedded semiconductor solution provider with more than 21,000 engineers and problem solvers in over 30 countries.

Requirements

• Bachelor's degree in Electrical Engineering, Applied Physics, or a related technical discipline.
• 8–10 years of engineering experience in semiconductor wafer fabrication, preferably involving yield, process integration, process engineering, product engineering, or device engineering.
• Strong understanding of semiconductor wafer fabrication processes and the relationship between process variation, device characteristics, defects, and electrical yield.
• Demonstrated ability to perform statistical analysis and solve complex manufacturing problems using large manufacturing datasets.
• Experience with statistical or data-analysis tools such as JMP or comparable platforms.
• Working knowledge of SPC, DOE, process capability, correlation and regression, hypothesis testing, and structured root-cause analysis.
• Ability to communicate complex technical conclusions clearly to engineering and manufacturing organizations.
• Demonstrated ability to lead cross-functional technical problem-solving efforts.
• Must meet applicable U.S. person requirements for ITAR access: U.S. citizen or national, lawful permanent resident, or protected individual as defined by 8 U.S.C. § 1324b(a)(3).

Nice To Haves

• Master's degree in Electrical Engineering, Applied Physics, or a related discipline.
• Experience correlating inline process or defect data with WAT/electrical data and wafer-sort/final yield.
• Experience with wafer-map and spatial-pattern analysis.
• Experience with semiconductor defect inspection or physical failure analysis.
• Experience creating automated yield-analysis or data-mining tools.
• Knowledge of semiconductor device physics and electrical test structures.
• Experience supporting technology or product ramps in a high-volume wafer fabrication environment.

Responsibilities

• Lead wafer-fab yield improvement initiatives, prioritize dominant yield-loss mechanisms, and turn analysis into actionable improvement projects.
• Analyze wafer probe maps, electrical test and bin data, inline metrology, defect inspection data, equipment and process history, and lot genealogy to identify systematic and random yield loss.
• Use correlation, regression, statistical analysis, wafer spatial analysis, trend analysis, and other data-mining techniques to identify relationships between process conditions and electrical yield.
• Lead root-cause investigations of process excursions, recurring yield degradation, wafer-level signatures, equipment effects, materials, and process interactions.
• Partner with Process and Equipment Engineering to develop physical process hypotheses from yield signatures and validate corrective actions.
• Define and execute structured experiments and DOE to validate suspected yield drivers and optimize process windows.
• Use SPC and process-capability analysis to identify process variation and opportunities for improved manufacturing control.
• Correlate WAT, wafer sort, inline process-monitoring, defect, and manufacturing data to identify yield improvement opportunities.
• Work with Failure Analysis teams to develop physical-analysis plans and translate findings into manufacturing actions.
• Develop analyses and engineering reports communicating yield trends, excursions, root causes, improvement opportunities, and project status.
• Lead cross-functional technical reviews for significant yield excursions and improvement programs.
• Support new-product or technology introduction by identifying yield risks, establishing baseline performance, and accelerating learning during manufacturing ramp.
• Mentor less-experienced engineers in statistical analysis, structured problem solving, yield analysis, and fab troubleshooting.
• Identify opportunities to improve fab-wide yield-analysis methods, data infrastructure, and problem-solving practices.

Benefits

• Medical, dental, and vision insurance from day one.
• Three weeks of accrued vacation per year.
• 13 paid holidays per year.
• 401(k) plan with employer matching up to 6%.
• Tuition reimbursement.
• Profit-sharing bonus.
• Competitive benefits package alongside salary; further information is provided during the hiring process.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior