Wafer Fab Yield Process Engineer

Renesas Electronics•Palm Bay, FL

5d•Onsite

About The Position

The Senior Wafer Fab Yield Engineer drives systematic yield improvement across semiconductor wafer fabrication. The role analyzes manufacturing, inline metrology, defect, wafer-level electrical test, and process data to identify yield-loss mechanisms, determine root causes, and lead sustainable corrective actions. It serves as a senior technical resource connecting fab process performance to device and product yield, working across Process Engineering, Equipment Engineering, Process Integration, Product/Test Engineering, Failure Analysis, Quality, and Manufacturing to improve yield, reduce variability, and resolve complex manufacturing problems. The position leads yield-improvement initiatives and investigations, performs statistical and spatial analyses, defines experiments, applies process-control methods, and communicates findings through engineering reports and technical reviews. It also supports product and technology introductions, mentors less-experienced engineers, and improves fab-wide yield-analysis methods and practices. This role is 100% onsite in Palm Bay, Florida. Candidates must meet applicable U.S. person requirements for ITAR access: U.S. citizen or national, lawful permanent resident, or protected individual as defined by 8 U.S.C. § 1324b(a)(3).

Requirements

Bachelor's degree in Electrical Engineering, Applied Physics, or a related technical discipline.
Significant engineering experience in semiconductor wafer fabrication, preferably involving yield, process integration, process engineering, product engineering, or device engineering.
Strong understanding of semiconductor wafer-fabrication processes and the relationship between process variation, device characteristics, defects, and electrical yield.
Demonstrated ability to perform statistical analysis and solve complex manufacturing problems using large manufacturing datasets.
Experience with statistical or data-analysis tools such as JMP or comparable platforms.
Working knowledge of SPC, DOE, process capability, correlation/regression, hypothesis testing, and structured root-cause analysis.
Ability to communicate complex technical conclusions clearly to engineering and manufacturing organizations.
Demonstrated ability to lead cross-functional technical problem-solving efforts.
Must meet applicable U.S. person requirements for ITAR access: be a U.S. citizen or national, lawful permanent resident, or protected individual as defined by 8 U.S.C. § 1324b(a)(3).

Nice To Haves

Master's degree in Electrical Engineering, Applied Physics, or a related discipline.
Experience correlating inline process and defect data with WAT/electrical data and wafer-sort/final yield.
Experience with wafer-map and spatial-pattern analysis.
Experience with semiconductor defect inspection and/or physical failure analysis.
Experience creating automated yield-analysis or data-mining tools.
Knowledge of semiconductor device physics and electrical test structures.
Experience supporting technology or product ramps in a high-volume wafer-fabrication environment.

Responsibilities

Lead wafer-fab yield-improvement initiatives, prioritize dominant yield-loss mechanisms, and turn analysis into actionable projects.
Analyze wafer probe maps, electrical test and bin data, inline metrology, defect-inspection data, equipment and process history, and lot genealogy to isolate systematic and random yield loss.
Perform correlation, regression, statistical, wafer-spatial, trend, and other data-mining analyses to identify relationships between process conditions and electrical yield.
Lead complex root-cause investigations into process excursions, recurring yield degradation, wafer-level signatures, equipment effects, materials, and process interactions.
Partner with Process and Equipment Engineering to develop physical process hypotheses from yield signatures and validate corrective actions.
Define and execute structured experiments and DOE to validate suspected yield drivers and optimize process windows.
Use SPC and process-capability analysis to identify process variation and opportunities for improved manufacturing control.
Correlate WAT, wafer sort, inline process-monitoring, defect, and manufacturing data to identify yield-improvement opportunities.
Work with Failure Analysis teams to develop physical-analysis plans and translate findings into manufacturing actions.
Develop analyses and engineering reports communicating yield trends, excursions, root causes, improvement opportunities, and project status.
Lead cross-functional technical reviews for significant yield excursions and improvement programs.
Support new-product and technology introductions by identifying yield risks, establishing baseline performance, and accelerating learning during manufacturing ramp.
Mentor less-experienced engineers in statistical analysis, structured problem solving, yield analysis, and fab troubleshooting.
Identify opportunities to improve fab-wide yield-analysis methods, data infrastructure, and problem-solving practices.