VLSI Design Verification Masters Level Intern

Hewlett Packard Enterprise•Ft. Collins, CO

2d•Hybrid

About The Position

Hewlett Packard Enterprise is hiring a master's-level intern to work with its team developing HPE Slingshot, an interconnect used in large HPC and AI systems. The intern will contribute to a switch or NIC ASIC verification project for a future generation of Slingshot, collaborating with experienced architects, logic designers, and verification engineers. The role offers exposure to industry-standard SystemVerilog and UVM verification techniques, technical design and debugging discussions, and agentic AI workflows used in engineering.

Requirements

Be pursuing a master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Have coursework in digital design and computer architecture.
Have experience with object-oriented programming.
Have strong analytical and problem-solving skills.
Have clear written and verbal communication skills.
Be willing to ask questions, explain reasoning, and participate in technical discussions.

Nice To Haves

Experience with a hardware description language such as Verilog, SystemVerilog, or VHDL.
Experience with Python, Perl, Tcl, or another scripting language.
Experience working in Linux development environments.
Academic, research, or personal projects involving digital hardware.
Experience working as part of a distributed team.
Experience with agentic AI coding tools and workflows.

Responsibilities

Develop SystemVerilog and UVM testbench components, including models, monitors, scoreboards, and checkers.
Write constrained-random tests.
Develop and analyze functional coverage to identify verification gaps.
Debug regression failures and help identify, log, and resolve logic bugs.
Work directly with ASIC designers and architects.
Use scripting, automation, and AI-assisted tools to improve the verification process.