Verification Platform Engineer, Platform Architecture

Apple • Austin, TX

3d • Onsite

About The Position

Apple’s Platform Architecture group develops the next generation of Apple hardware and the tools to make it possible. Our team builds high-performance verification systems that accelerate the development of Apple silicon. We aim to push the boundaries of pre-silicon validation with simulation solutions that apply and extend principles from hardware emulation. This role bridges Apple's next-generation platform technology with DV methodology and tooling. We are seeking an engineer with background in Design Verification who is interested in cutting-edge verification techniques and comfortable rapidly prototyping solutions. In this role, you will enable transformational improvements to simulation throughput for DV workflows through testbench design, infrastructure improvements, and platform R&D. Own engagements with silicon engineering groups to evaluate, integrate, and maintain high performance RTL simulation tooling. Modify testbench and design RTL for tool compatibility and simulation efficiency. Use internal and external EDA tools (e.g., RTL simulation tools, Logic Equivalence Checking [LEC], wave dumps, design libraries) to diagnose issues and explore design alternatives. Design and integrate infrastructure improvements for faster simulation turnaround after RTL changes. Partner closely (or embed) with internal teams for focused, high-impact engagements. Occasionally travel (approximately once a year) to collaborate with development groups within the US.

Requirements

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent practical experience).
• Experience with SystemVerilog and EDA tooling.
• Experience with software development (e.g., using C++) and scripting (e.g., Perl or Python).
• Deep hands-on experience in Design Verification methodologies (UVM, DPI-C, testbench architecture).
• Experience applying LEC, linting / static analysis tools, waveform debugging, and simulation / emulation flows.
• Strong understanding of SystemVerilog simulation semantics (events, time, glitches); intuitive grasp for hardware representation (clocks, resets, latches).
• Strong communication skills, with a proven history of cross-functional collaboration across silicon engineering, design verification, and EDA development teams and organizational boundaries.

Nice To Haves

• Master’s degree in Computer Engineering, Electrical Engineering, or another hardware-related field.
• 3+ years of relevant experience.
• Experience with software optimization, high-performance computing (HPC), co-simulation architectures, or hardware acceleration / emulation.
• Development of agentic pipelines, graphs, skills, or similar work enabling AI productivity for other engineers.

Responsibilities

• Enable transformational improvements to simulation throughput for DV workflows through testbench design, infrastructure improvements, and platform R&D.
• Own engagements with silicon engineering groups to evaluate, integrate, and maintain high performance RTL simulation tooling.
• Modify testbench and design RTL for tool compatibility and simulation efficiency.
• Use internal and external EDA tools (e.g., RTL simulation tools, Logic Equivalence Checking [LEC], wave dumps, design libraries) to diagnose issues and explore design alternatives.
• Design and integrate infrastructure improvements for faster simulation turnaround after RTL changes.
• Partner closely (or embed) with internal teams for focused, high-impact engagements.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior