Verification Engineer – Silicon / Semiconductor

Simple SolutionsSanta Clara, CA

About The Position

We are seeking a Verification Engineer to join our silicon development team, responsible for ensuring the functional correctness and quality of complex ASIC/SoC designs. This role is critical in validating next-generation chips used in high-performance computing, AI/ML, networking, or consumer electronics. You will work closely with design, architecture, and validation teams to develop robust verification environments and drive coverage closure.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
  • 3–10+ years of experience in ASIC/SoC verification
  • Strong expertise in SystemVerilog and UVM methodology
  • Experience with RTL design concepts (Verilog/VHDL)
  • Solid debugging skills in simulation environments
  • Experience with EDA tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)
  • Understanding of functional coverage and verification metrics

Nice To Haves

  • Experience with formal verification tools
  • Knowledge of protocols (PCIe, Ethernet, AXI, DDR, USB, etc.)
  • Scripting skills in Python, Perl, or Tcl
  • Experience with emulation or FPGA prototyping
  • Exposure to low-power verification (UPF/CPF)
  • Background in AI/ML accelerators or GPU architectures

Responsibilities

  • Develop and execute verification plans for ASIC/SoC components and subsystems
  • Build and maintain SystemVerilog/UVM-based testbenches
  • Create directed and constrained-random tests to validate design functionality
  • Debug and root-cause RTL issues in collaboration with design engineers
  • Drive functional coverage and ensure verification completeness
  • Perform regression testing and analyze results for failures and gaps
  • Develop and use assertions (SVA) for design verification
  • Contribute to verification methodology improvements and automation
  • Support post-silicon validation teams with test scenarios and debug insights
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