Validation Engineer III

TekWissen • San Jose, CA

1d • Onsite

About The Position

TekWissen is seeking a senior-level contractor to lead production test development for system-on-chip (SoC) devices integrating copackaged optics (CPO) SerDes interfaces. The role focuses on ATE program development, DFT/BIST enablement, yield and quality optimization, and high-volume manufacturability. It requires strong knowledge of SerDes and protocols such as UCIe and PCIe, including the ability to translate characterization results into robust multisite production tests. Python-based automation and data analytics are essential; familiarity with AI-assisted tools for test development and data triage is a plus.

This is a 12-month temporary, onsite assignment in San Jose, California. The contractor will develop, integrate, and maintain wafer-sort and final-test programs; establish production test coverage for SerDes PHY and protocol features; optimize multisite testing and test time; correlate bench and characterization results with ATE; integrate DFT features; and implement protocol-related production checks. The role also builds Python tooling for ATE control and test-data analysis, collaborates with design, firmware, DFT, product engineering, OSAT/probe, and signal-integrity teams, and documents and supports test releases and sustaining engineering.

Requirements

• Hands-on experience developing tests on leading ATE platforms, such as Advantest V93K/AC+ or Teradyne UltraFLEX/UltraFLEXplus, including timing sets, DC/AC measurements, and multisite testing.
• Strong understanding of SerDes/PHY fundamentals, including equalization, CDR, CTLE/DFE, PRBS/BER, margining, jitter/eye constraints, and on-die BIST integration.
• Proficiency in Python for automation and data analytics, including experience with STDF parsing, visualization, and automated SPC/anomaly detection.
• Solid DFT background, including scan/ATPG patterns, boundary scan, MBIST/LBIST, JTAG access, WGL/STIL pattern formats, and pattern bring-up on ATE.
• Working knowledge of UCIe and PCIe from a production-test perspective, including link checks through firmware/test hooks, error counters, and compliance indicators.
• Excellent documentation, cross-functional communication, and problem-solving skills.

Nice To Haves

• Familiarity with AI-assisted tools for test development and data triage.
• Experience with UCIe and PCIe Gen5/Gen6.

Responsibilities

• Develop, integrate, and maintain wafer-sort and final-test ATE programs for SoC SerDes with copackaged optics.
• Define and implement production test coverage for SerDes PHY and protocol features, including PRBS, loopback, margining, FEC, CDR lock, and equalizer settings, using on-die BIST/DFT and ATE instrumentation.
• Implement and optimize multisite strategies, parallel test execution, guardbanding, and test-time reduction while meeting quality and test-coverage goals.
• Correlate bench and characterization results to ATE; develop golden-unit flows, establish limits, manage characterization-to-production handoffs, and close gaps.
• Integrate scan/ATPG, boundary scan, MBIST/LBIST, and JTAG features into production flows; manage pattern conversion, timing sets, and pin maps.
• Implement UCIe/PCIe production checks, including link-training emulation, LTSSM state verification through firmware or test hooks, compliance counters, and error injection and monitoring.
• Build Python-based tooling for ATE control, data parsing, STDF analytics, dashboards, and automated limit updates; integrate with MES/SPC and CI pipelines.
• Collaborate with silicon design, firmware, DFT, product engineering, OSAT/probe, and SI teams to resolve issues and qualify ECOs and revisions.
• Document test plans, specifications, vector maps, limits, and release notes; train operations teams and support sustaining engineering.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed