TPM Lead

Normal Computing Corporation • Palo Alto, CA

4d

About The Position

Normal Computing is an applied AI company developing foundational hardware and software for the semiconductor industry, AI infrastructure, and broader systems. The TPM Lead partners with engineering leads to translate company objectives into actionable milestones, own schedules across the full silicon development lifecycle, communicate project status to engineering executives, and help resolve issues across teams. The role is responsible for ensuring projects ship on time.

The position coordinates silicon development work across teams in Mountain View, New York, London, Zurich, and Copenhagen. It defines metrics and dashboards to track progress, identifies and mitigates delivery and quality risks, and synthesizes technical status, trade-offs, and risks into clear executive updates.

Requirements

• 10+ years of experience in semiconductor development.
• 3+ years as a TPM or program lead on complex ASIC or SoC architectures.
• Excellent communication and stakeholder management skills, including the ability to influence without authority.
• Experience in companies with complex software and hardware integration.
• A proven track record managing internationally distributed engineering teams.
• Proficiency with program management tools such as Jira, Asana, or Linear.
• Experience with every element of the silicon lifecycle, from architecture and RTL generation through verification, tapeout, bring-up, and post-silicon validation.
• Ability to think out of the box to find solutions.

Nice To Haves

• Ph.D. in an electrical engineering discipline.
• Familiarity with chiplets and 3D packaging.
• Expertise using Linear for program management tracking.
• Familiarity with heterogeneous systems used for AI inference.
• Experience working with external silicon foundries, Tier II vendors, and OSAT vendors.
• Experience working at a silicon startup.

Responsibilities

• Break down company objectives into actionable milestones across the engineering organization.
• Own the schedule across the silicon development lifecycle, including architecture, micro-architecture, RTL generation, verification, logic synthesis, design for test, physical design, physical verification, tapeout, packaging, post-silicon testing, bring-up, and post-silicon validation.
• Coordinate development efforts across teams in Mountain View, New York, London, Zurich, and Copenhagen.
• Define metrics and create dashboards and other mechanisms to surface information and track progress.
• Identify and mitigate risks to delivery schedules and quality.
• Synthesize complex technical status, trade-offs, and risks into clear updates for executive leadership.
• Help resolve issues across teams.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed