Timing/Power Methodology Architect

Advanced Micro Devices, Inc•Austin, TX

12h

About The Position

As part of AMD’s physical design methodology team, this role helps define timing, power, and clocking methodologies for next-generation, high-performance cores, graphics, and machine-intelligence chips. The position works across multiple divisions to drive physical design methodology optimizations across libraries, technology, flows, and design. The team’s projects span products from low-power APUs to supercomputers.

Requirements

Mastery of logic, circuit design, and CAD tools for high-performance design.

Nice To Haves

MS or PhD degree in Electrical Engineering.
Design experience in sub-micron processes.
Familiarity with CPU and/or GPU architecture.
Hands-on experience with power-analysis and measurement tools such as Prime Power and/or Power-Artist.
Experience with high-performance clocking.
Experience with STA methodologies for timing closure, OCV, and other advanced statistical margining techniques.
Proficiency in scripting languages such as Perl, Tcl, or Python.
Proficiency in data analysis and interpretation.

Responsibilities

Drive PVT corners and frequency targets while considering product performance modes and guard bands.
Drive IP physical implementation recipes from synthesis through route to achieve the best performance per watt.
Co-develop RTL architecture and physical design to identify bottlenecks.
Drive budgeting, measurement, analysis, and tracking of power consumption.
Establish global methodologies and best-known physical implementation recipes for optimal performance per watt across library, flow, synthesis, and place-and-route environments.
Drive global and local clock-distribution best practices, balancing skew, power, and jitter.
Create guidelines for clocking, timing, and power sign-off methodologies.