Technical Staff Engineer - Design Implementation

Microchip • Chandler, AZ

2d • Onsite

About The Position

We are seeking a senior silicon implementation engineer with deep expertise in methodology development and implementation flows for next generation 12nm silicon, with particular focus on hierarchical SoC execution, timing convergence, and multi-die design enablement. The successful candidate will play a central role in shaping scalable RTL-to-silicon methodologies and driving robust implementation practices across complex SoC programs.

Requirements

• BS or MS in Electrical Engineering or related field with 14+ years of experience in SoC implementation activities
• Strong hands-on expertise in synthesis, UPF specification, timing closure, hierarchical implementation, and low-power digital design flows.
• Hands-on experience in industry standard EDA tools: Genus/iSpatial/Design Compiler/Fusion Compiler Tempus/Primetime Prime Power/VCLP/RTL architect Conformal/Formality
• Deep understanding of SoC timing architecture, including clocking strategy, constraint development, timing budgeting, and block-to-top convergence
• Ability to incorporate system level timing specifications into implementation constraints needed for synthesis and timing closure
• Good background in digital microarchitecture, RTL coding and front-end to implementation handoff quality.
• Strong cross-functional communication skills, and demonstrated technical leadership in ambiguous environments
• Demonstrated ability to build new process flows and scale implementation methodologies across teams.
• Proactively build new methodologies when existing flow do not scale.
• Experience working in first-generation product environments where flows, margins, and best practices must be established.

Responsibilities

• Develop and deploy advanced SoC implementation flows for complex chips involving hierarchical design planning, logic synthesis, timing closure, power analysis, and low-power implementation methodologies like UPF specification
• Define top-level timing methodologies across IPs, subsystems, and full-chip integration to ensure predictable convergence to signoff targets
• Drive design implementation methodology tailored for multi-die integration, timing constraints strategy, and integration flows
• Influence design partitioning decisions by evaluating their impact on implementation complexity, timing closure, power, yield, and scalability
• Develop effective timing constraints for complex blocks and SoCs, including clock definition, exception strategy, interface budgeting
• Work well with physical design team to drive floorplanning decisions and clock tree constraints to meet key performance goals
• Mentor engineers on design implementation flows, timing closure strategies, and multi-die design best practices

What This Job Offers

• Job Type: Full-time
• Career Level: Senior