Technical Program Manager

Unconventional, Inc.•Mountain View, CA

About The Position

The posting describes a foundational digital design role on Unconventional’s small, multidisciplinary R&D team, focused on developing a more energy-efficient computing platform for AI. The role involves defining and integrating digital SoC components, implementing and validating RTL, supporting verification, and coordinating design handoffs to physical implementation teams. It also includes technical guidance for junior engineers and contributions to design methodologies and infrastructure. Note: The supplied title is “Technical Program Manager,” but the role description itself identifies the position as “Member of Technical Staff, Digital Design Engineer” and focuses on digital ASIC/SoC design.

Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
At least 8 years of industry experience in digital ASIC/SoC design.
Expertise in Verilog RTL coding and digital design fundamentals.
Familiarity with standard EDA tools for simulation, synthesis, linting, and CDC analysis.
Understanding of the full ASIC design flow, from specification to tape-out.
Excellent written and verbal communication skills.
Ability to lead junior engineers toward team goals and assist with their skill development.

Nice To Haves

Experience creating digital designs, including synchronous and asynchronous logic, state machines, and bus protocols.
Experience developing scripts or tooling for design automation.
Experience optimizing designs for performance, power, or area.
Experience with modern design methods, including generative AI code development platforms.
Experience with analog mixed-signal technology and interfaces.

Responsibilities

Lead detailed micro-architecture definition and top-level integration of digital blocks, including CPU, memory subsystems, and interfaces.
Own integration of third-party IP into the main SoC fabric.
Provide technical guidance and mentorship to junior digital design engineers.
Contribute to design-methodology best practices, code reviews, and quality assurance processes.
Enhance and contribute to early-stage design infrastructure for rapid tapeout.
Drive and perform hands-on RTL design for complex, timing-critical SoC blocks and digital interfaces while meeting power, performance, and area targets.
Implement and debug key digital interfaces.
Perform initial synthesis and formal verification (LEC) to ensure the design is routable and meets frequency targets.
Create block-level timing constraints.
Run and resolve RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks using industry-standard tools.
Participate in block-level verification planning and help develop a robust verification environment.
Triage and debug complex simulation failures to ensure functional correctness.
Facilitate handoff between internal design and internal or external physical implementation teams for synthesis and timing closure.