Technical Manager, Physical Design Verification Lead (7264)

TSMC•San Jose, CA

26d•$153,000 - $230,000•Onsite

About The Position

TSMC Technology Inc. is at the forefront of semiconductor innovation, delivering cutting-edge solutions that power the next generation of technology. We are seeking a highly experienced and motivated Physical Design Verification Lead to join our dynamic team, working closely with a key customer on advanced designs in N2P/A14 technology nodes. This is an exceptional opportunity to drive critical verification efforts on state-of-the-art technology nodes and contribute to successful production tapeouts.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
10-20 years of hands-on experience in physical implementation and verification roles.
Demonstrated expertise with major Electronic Design Automation (EDA) tools (e.g., Innovus/ICC2, Calibre) and established design flows.
Extensive experience in chip integration and sign-off procedures.
Proven experience with advanced technology nodes, specifically TSMC N7 or below.
Proficiency in scripting languages, particularly TCL, Perl, and Python, for automation and flow enhancement.
Ability and willingness to work full-time at a customer site located in the South Bay area.

Nice To Haves

Direct experience with TSMC N2 technology nodes.
In-depth knowledge of CPU implementation methodologies.
Expertise in advanced timing sign-off methodologies and techniques.
A strong track record of successful production tapeouts for multi-million gate designs.
Prior experience leading physical verification efforts or small teams.

Responsibilities

Lead and execute end-to-end physical design verification for CPU blocks, culminating in successful production chip tapeouts.
Collaborate closely with the STA team to implement Engineering Change Orders (ECOs) for critical timing closure.
Perform in-depth analysis and resolution of Signal EM/Noise and Power IR/EM issues.
Manage comprehensive analysis and cleanup for all physical verification checks, including DRC, LVS, ERC, and Antenna violations.
Achieve final physical verification sign-off across all design metrics.
Oversee the implementation of customized Clock Tree Structures (CTS) and advanced Place & Route strategies.
Optimize block-level floorplans, meticulously analyzing and ensuring high-quality design partitioning.
Provide technical leadership and mentorship to junior engineers.