System Validation Engineer (NCG 2026)

Astera LabsSan Jose, CA

About The Position

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
  • Strong academic foundation in circuit analysis, signals and systems, electromagnetics, or high‑speed digital design through coursework and labs
  • Familiarity with PCIe®, CXL™, or Ethernet standards
  • Familiarity with fundamental signal‑integrity concepts such as eye diagrams, jitter, noise, impedance, and transmission lines
  • Exposure to electrical lab equipment (e.g., oscilloscopes, logic analyzers, network analyzers)
  • Experience using scripting or programming languages such as Python, MATLAB, TCL, or C/C++
  • Comfortable working with lab tools and debugging hardware
  • Strong analytical and communication skills

Nice To Haves

  • Exposure to post-silicon validation or bring-up of connectivity IP blocks
  • Knowledge of signal integrity analysis and eye diagram interpretation
  • Familiarity with Linux systems, shell scripting, and version control (Git)
  • Understanding of AI workloads and how interconnect bandwidth impacts performance

Responsibilities

  • Hands-on experience with industry-leading connectivity solutions for AI infrastructure
  • Mentorship from engineers at the forefront of silicon innovation
  • Exposure to the full lifecycle of chip development—from tape-out to deployment
  • Opportunity to contribute to products used by top hyperscalers and cloud providers

Benefits

  • The base salary range for this role is $130,000 - $150,000 annually.
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