System Architecture Engineer Leader (Hardware Board Design) (Onsite)

Cisco•Milpitas, CA
•$194,600 - $285,700•Onsite

About The Position

Cisco Silicon One and the Service Provider Routing Hardware Engineering team develop complex, high-performance silicon and next-generation networking hardware. The team designs Cisco 8000 Series routers, powered by Cisco Silicon One ASICs, for the scale, performance, and efficiency required by critical infrastructure. This role collaborates with board design, ASIC, signal integrity, power, software, mechanical, thermal, manufacturing, systems, and supplier teams to define, design, validate, and release networking products. As a senior technical lead in hardware board design, this individual contributor role shapes multi-year hardware architecture, design standards, and technical strategy for major networking products. The engineer leads cross-functional initiatives, addresses complex technical problems, influences senior leaders, and guides senior technical talent; people management is not required. The role is based near Cisco’s Milpitas, California office and requires commuting to the lab five days per week.

Requirements

  • Bachelor’s degree in Electrical Engineering or Computer Engineering and 11 or more years of experience; or a master’s degree in either field and 7 or more years of related experience; or a Ph.D. in either field and 4 or more years of related experience.
  • Experience in hardware board design and system architecture, taking high-performance products from concept through production, including PCIe, Ethernet, DDR, SerDes, and advanced thermal and EMI management.
  • Experience with high-speed digital design, signal and power integrity, power distribution, and reliability testing.
  • Hands-on experience using Cadence design tools and advanced laboratory instrumentation, such as oscilloscopes and logic or spectrum analyzers.
  • Experience leading complex, multi-site, cross-functional engineering initiatives and partnering with silicon vendors and contract manufacturers to solve high-impact technical challenges.

Nice To Haves

  • Experience with advanced networking systems, ASICs, FPGAs, high-speed memory, multi-gigabit SerDes, and advanced packaging.
  • Experience in co-packaged or near-packaged optics, signal and power integrity budget analysis, ultra-high-speed signaling, and next-generation power delivery.
  • Hands-on experience with Cadence Concept/Allegro, HyperLynx, ANSYS, Keysight ADS, and laboratory equipment such as VNA, TDR, high-bandwidth oscilloscopes, and protocol analyzers.
  • Experience creating Python test scripts to streamline validation and design tasks.
  • An analytical, methodical approach to decomposing complex issues, evaluating empirical evidence, and documenting clear, actionable conclusions.
  • A record of effective cross-functional collaboration and driving initiatives forward.
  • Experience influencing senior technical and business leaders across organizational boundaries, with strong written, verbal, and executive-level communication skills.
  • Experience mentoring senior engineering talent.
  • A record of delivering large-scale products and technical innovations, supported by patents, influential publications, or active standards participation.
  • A master’s degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.

Responsibilities

  • Define long-term hardware architecture, power-delivery strategy, design standards, and technology roadmaps for high-performance networking systems.
  • Lead major, multidisciplinary hardware initiatives from early concept through product release and customer delivery.
  • Serve as a senior escalation point for novel or high-risk architectural, signal integrity, power integrity, reliability, field, and manufacturing issues.
  • Develop and communicate technical strategies that align multiple business units and engineering disciplines.
  • Establish reusable methods, constraints, verification practices, and quality standards for board design.
  • Guide senior engineers and technical leaders through architecture reviews, design tradeoffs, and complex investigations.
  • Represent hardware engineering in executive reviews, strategic supplier discussions, standards activities, and selected external technical engagements.
  • Anticipate industry and technology shifts and recommend investments in future hardware capabilities.
  • Drive decisions using simulations, laboratory evidence, product data, and an understanding of business impact.

Benefits

  • Medical insurance
  • Dental insurance
  • Vision insurance
  • 401(k) plan with Cisco matching contribution
  • Paid parental leave
  • Short- and long-term disability coverage
  • Basic life insurance
  • Paid holidays and a floating holiday for non-exempt employees
  • Birthday day off, year-end holiday shutdown, and personal wellness days
  • Paid vacation or flexible vacation time off, depending on employee classification
  • Paid sick time
  • Additional paid time away may be requested for critical or emergency family matters
  • Optional paid volunteer days
  • Annual bonuses may be available for non-sales roles
  • Eligible employees may receive Cisco restricted stock unit grants
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