SW engineer - Silicon CAD tool development

Intel•Us, CA

4d•Hybrid

About The Position

Intel is seeking a motivated mid-level CAD/EDA Software Engineer to join the Silicon Chassis Automation Tool team. In this hands-on role, you will work closely with the tool lead to develop a chassis automation tool and own key subsystems. Chassis refers to non-compute infrastructure in any SoC, which provides essential platform services and typically includes interconnects, protocol bridges, clock/reset/power, security, debug/trace/analytics (DTA), RAS error logic, address maps, firmware tables, and more. The chassis automation tool collects user requirements and translates them into detailed parameters representing topology, then generates RTL, register definitions, integration, and verification collateral for the chassis using highly parameterized and configurable sub-components. Why This Role Is Exciting Build a brand new automation platform by defining the tool, schema, and methodology from the ground up Directly influence next-generation SoC chassis architectures and delivery. Position Overview: You will work directly with the tool lead and partner with RTL design, verification, and SoC integration teams to code the architectural rules of the interconnect and develop a reliable, testable automation framework that produces expected results. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.

Requirements

Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 4+ years of experience in CAD/EDA tooling or design automation, or a Master's degree in a related field with 3+ years of experience
3+ years of Python or a similar language, with hands-on experience building software systems or frameworks, including packaging, testing, and CLI tool development
Experience designing and validating structured schemas using formats such as JSON or YAML
Knowledge of software engineering fundamentals including version control (Git), code reviews, unit/integration testing, and CI/CD practices

Nice To Haves

Understanding of digital SoC design concepts, including RTL hierarchy, synthesis flows, and parameterized IP design
Working knowledge of SystemVerilog to understand and validate generated design outputs
Experience with Network-on-Chip (NoC) architectures or high-performance interconnect protocols such as AXI, CHI, PCIe, UCIe, or similar
Familiarity with IP packaging, configuration, and integration methodologies, including standards such as IP-XACT
Exposure to industry EDA tools and design flows
Knowledge of graph-based algorithms or data structures relevant to topology generation, connectivity modeling, or routing problems
Experience in GUI development with modern UI frameworks such as Qt/QML, React, Electron etc.
Strong understanding of object-oriented design, design patterns, and software architecture principles.

Responsibilities

Develop a chassis automation tool that meets requirements across multiple SoC programs, ensuring scalability, maintainability, and extensibility
Understand automation tool requirements and build tooling and infrastructure to translate those requirements into working code, generating outputs such as RTL, RDL, verification collateral, timing, and integration artifacts
Integrate with silicon frontend and backend tool flows to enable robust validation and quality checks across generated artifacts (e.g., RTL, Verilog, SDC, RDL), ensuring correctness and consistency
Work closely with the tool lead, architecture, RTL design, verification, and SoC integration teams to ensure the tool accurately produces outputs that meet downstream expectations
Follow and improve best practices in software design, testing, and maintainability, elevating overall team effectiveness
Set up and maintain the CI/CD regression pipeline
Implement specific rule functions, write unit tests, and extend coverage as needed