Staff Software Engineer — SubSystem Integration Test (SSIT)

Qualcomm•Raleigh, NC

5d•$142,600 - $213,800

About The Position

As part of the AISW engineering team at Qualcomm, you will be the software system integration test (SSIT) engineer for the Delegates portfolio — ONNX Runtime (QNN Execution Provider), ExecuTorch (HTP/QNN backend), and TFLite / LiteRT. You will own subsystem-level validation at the feature development stage — working side-by-side with software engineers to define test strategy early, build targeted test content, and ensure each feature is solid before it transitions to QA and System Integration Test (SIT). This is a shift-left quality role: you are a co-owner of feature quality from inception, not a downstream gatekeeper.

Requirements

Bachelor's degree in Computer Science, Engineering, Information Systems, or related field and 4+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience.
Master's degree in Computer Science, Engineering, Information Systems, or related field and 3+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience.
PhD in Computer Science, Engineering, Information Systems, or related field and 2+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience.
Bachelor's + 8 years or Master's + 6 years in Software Engineering, Computer Science, Systems Engineering, or related field
Strong Python; proven hands-on experience building automated test frameworks (PyTest or equivalent)
C/C++ reading proficiency sufficient to debug delegate and runtime issues at the source level
Demonstrated experience in subsystem or integration testing within a hardware/software product development cycle
Experience with CI/CD platforms (Jenkins, GitHub Actions, or equivalent) and integrating test automation into build pipelines
Strong analytical and debugging skills with ability to isolate failures across multi-layer software stacks

Nice To Haves

Experience validating ML inference frameworks — ONNX Runtime, ExecuTorch, TFLite / LiteRT, or equivalent
Hands-on experience with Qualcomm QNN, HTP/DSP, or Snapdragon SoC-based on-device validation
Familiarity with model accuracy validation: quantization correctness, op-level numerical comparison, and tolerance analysis
C/C++ proficiency for development and debug of ORT unit tests
Cross-platform test experience: Linux, Android, and Windows (ARM64 or x86)
Experience with JIRA defect tracking and Agile/scrum development practices

Responsibilities

Partner with delegate engineers from feature inception to define testability requirements, acceptance criteria, and subsystem test plans covering ORT QNN-EP, ExecuTorch HTP backend, and LiteRT delegate
Own SSIT test strategy per feature: scope, entry/exit criteria, coverage targets, and risk-based prioritization — aligned with the development team before implementation begins
Embed in sprint planning, design reviews, and code reviews to ensure features are architected for testability from day one
Develop and maintain automated test content targeting the subsystem boundary: op and feature coverage, numerical accuracy, model-level functional correctness, and backend interface contracts
Validate on-device behavior on Snapdragon SoCs using HIL infrastructure, covering functional correctness, latency, and memory under real hardware conditions
Build Python/PyTest-based test suites integrated into the Delegates CI pipeline; ensure SSIT gates are enforced on every code change
Develop and leverage AI-assisted tooling and agentic workflows (Claude Code, GitHub Copilot) to accelerate test content generation, coverage analysis, and failure triage
Triage failures and isolate root causes across the delegate stack — ML framework → QNN runtime → HTP hardware — and drive resolution with development owners
Flag integration risks early during feature development; distinguish subsystem-level issues from upstream framework bugs and downstream backend or system integration issues
Define and own handoff criteria from SSIT to QA and SIT: documented test results, known issues, coverage gaps, and risk summaries that give downstream teams a clear picture of feature readiness
Serve as the primary technical liaison between the Delegates development team and QA/SIT — translating feature context into actionable test guidance for downstream teams
Maintain traceability between SSIT artifacts and QA/SIT test plans via JIRA; feed defects found in QA/SIT that trace to subsystem gaps back into SSIT coverage
Sets the SSIT quality strategy and test architecture for the full Delegates portfolio at Staff level — operates independently with minimal direction
Co-owns feature quality from day one alongside development engineers; defines what 'done' means from a subsystem validation standpoint before handoff to QA
Primary technical bridge between the Delegates development team and downstream QA/SIT — owns the clarity and completeness of that interface
Mentors junior and senior SSIT engineers; establishes team norms for test coverage, triage discipline, and handoff documentation standards
Collaborates with CI/Build/Release engineers to ensure SSIT automation is embedded in the delivery pipeline and readiness signals are visible to Program Management