Staff Engineer, Test Development

Celestica•San Jose, CA

17d

About The Position

Celestica is seeking a Staff Engineer, Hardware Test and Validation to provide senior technical and engineering leadership for validation and characterization of complex, high-performance hardware platforms. The Staff Engineer serves as a technical authority across hardware validation, signal integrity, power integrity, and high-speed interface technologies. The role defines validation strategies, establishes engineering methodologies and best practices, guides complex technical investigations, and influences product architecture and design decisions across multiple programs. It combines hands-on laboratory expertise with system-level architecture, technical leadership, customer engagement, and strategic engineering decisions. The position provides leadership across programs and engineering teams, setting technical direction, identifying cross-program risks, and shaping architecture-level decisions based on measurement and analysis. The Staff Engineer leads complex initiatives, serves as an escalation point for difficult SI, PI, interface, and system-level hardware problems, mentors engineers, communicates with customers and senior technical stakeholders, and develops validation capabilities and engineering roadmaps. The role remains technically hands-on while connecting detailed engineering execution with product architecture, customers, and the broader engineering organization. Duties are performed in a normal office environment and may involve extended sitting, sustained visual concentration on computer monitors or detailed data, and frequent repetitive manual movements. Occasional travel may be required.

Requirements

Typically 12+ years of progressive experience in hardware design, hardware validation, signal integrity, power integrity, electrical characterization, or related disciplines; the posting also lists 7 to 10 years of related experience for similar job roles.
Demonstrated experience operating as a senior technical leader on complex hardware development programs.
Deep understanding of high-speed digital design and signal integrity, including transmission lines, impedance, reflections, insertion and return loss, crosstalk, jitter, equalization, BER, and timing margin.
Strong hands-on expertise with PCIe and Ethernet electrical validation and system-level troubleshooting.
Strong knowledge of high-speed SerDes architectures, NRZ and PAM4 signaling, and channel characterization.
Deep understanding of power delivery and power integrity, including voltage regulation, PDN behavior, transient response, ripple/noise, sequencing, and high-current power rails.
Extensive experience using high-bandwidth oscilloscopes, BERTs, VNAs, TDR/TDT equipment, spectrum analyzers, protocol analyzers, electronic loads, power analyzers, and other advanced laboratory instrumentation.
Ability to interpret schematics, PCB layouts, design specifications, simulation results, standards, and component documentation.
Demonstrated ability to lead complex root-cause investigations spanning multiple engineering disciplines.
Experience with Python or similar programming and scripting languages for test automation and data analysis.
Strong written and verbal communication skills, including the ability to explain complex technical subjects to engineering teams, senior leadership, customers, and partners.
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or an equivalent combination of education and experience.

Nice To Haves

Master's degree.
Experience with PCIe Gen5/Gen6 electrical validation and compliance.
Experience with 100G/200G/400G/800G Ethernet.
Advanced SerDes characterization experience.
Experience with PAM4 and NRZ signaling.
Experience with eye diagram, jitter, BER, bathtub-curve, and link-margin analysis.
Experience with S-parameter and VNA-based channel characterization.
Experience with TDR/TDT and impedance characterization.
Experience with high-speed PCB and connector characterization.
Experience with power-integrity and PDN simulation/measurement correlation.
Experience with high-current CPU, GPU, ASIC, FPGA, and accelerator power delivery.
Experience with protocol and link-layer debugging.
Experience with Python-based laboratory automation and data analytics.
Experience with server, networking, storage, AI/ML, or high-performance computing platforms.
Experience developing and qualifying complex multi-board systems.

Responsibilities

Serve as the primary technical authority for hardware validation, signal integrity, and power integrity.
Define global validation strategies and engineering standards, and influence early product architecture to mitigate system-level risks.
Lead schematic and PCB reviews and improve laboratory infrastructure and simulation-to-measurement correlation.
Direct signal-integrity characterization of advanced interconnects, including PCIe Gen5/Gen6 and 100G–800G Ethernet.
Perform advanced testing of NRZ and PAM4 signaling, including eye diagrams, jitter, and channel loss.
Lead power delivery network validation for high-performance CPU, GPU, and ASIC workloads.
Characterize transient response, ripple, and rail stability, including interactions among power integrity, signal integrity, and thermal behavior.
Lead structured root-cause investigations into complex hardware, firmware, and system-level failures.
Partner with cross-functional and supplier teams to isolate faults and resolve critical customer escalations.
Develop scalable Python-based test automation frameworks for instrumentation control and data acquisition.
Standardize validation infrastructure to improve engineering productivity and accelerate data-driven decisions.
Mentor senior engineers and guide cross-functional teams through product milestones.
Align conflicting technical priorities and influence architecture-level engineering decisions.
Build strategic relationships with vendors and partners, define future validation roadmaps, and promote engineering rigor.
Recognize cross-program technical risks and establish scalable solutions.
Lead complex technical initiatives involving multiple engineering disciplines and organizations.
Communicate complex technical subjects effectively to customers and senior technical stakeholders.
Translate emerging technologies and customer requirements into validation capabilities and engineering roadmaps.
Balance product execution with longer-term improvements in engineering methodology, automation, laboratory capability, and organizational expertise.