Staff Engineer, Test Development

Celestica International LP•San Jose, CA

18d

About The Position

Celestica is seeking a Staff Engineer to provide senior technical and engineering leadership for validation and characterization of complex, high-performance hardware platforms. The role serves as a technical authority across hardware validation, signal integrity, power integrity, and high-speed interface technologies. It defines validation strategies, establishes engineering methodologies and best practices, guides complex technical investigations, and influences product architecture and design decisions across multiple programs. The successful candidate brings hands-on expertise in signal integrity, power delivery and power integrity, PCI Express, Ethernet, and high-speed SerDes technologies, together with the ability to lead and mentor engineering teams, influence cross-functional organizations, and engage technically with customers and technology partners. The role spans laboratory measurements, system-level architecture, technical leadership, and strategic engineering decisions. The Staff Engineer remains technically hands-on while bridging detailed engineering execution, product architecture, customers, and the wider engineering organization. This position is based in San Jose, California. Duties are performed in a normal office environment and may require occasional travel. The role may involve extended sitting and sustained visual concentration, as well as frequent repetitive manual movements such as data entry and computer use.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or an equivalent combination of education and experience.
Typically 12+ years of progressive experience in hardware design, hardware validation, signal integrity, power integrity, electrical characterization, or related disciplines; the posting also lists 7 to 10 years of related experience in a separate Typical Experience statement.
Demonstrated experience as a senior technical leader on complex hardware development programs.
Deep understanding of high-speed digital design and signal integrity, including transmission lines, impedance, reflections, insertion and return loss, crosstalk, jitter, equalization, BER, and timing margin.
Strong hands-on expertise with PCIe and Ethernet electrical validation and system-level troubleshooting.
Strong knowledge of high-speed SerDes architectures, NRZ and PAM4 signaling, and channel characterization.
Deep understanding of power delivery and power integrity, including voltage regulation, PDN behavior, transient response, ripple/noise, sequencing, and high-current power rails.
Extensive experience with advanced laboratory instrumentation, including high-bandwidth oscilloscopes, BERTs, VNAs, TDR/TDT equipment, spectrum analyzers, protocol analyzers, electronic loads, and power analyzers.
Ability to interpret schematics, PCB layouts, design specifications, simulation results, standards, and component documentation.
Demonstrated ability to lead complex root-cause investigations spanning multiple engineering disciplines.
Experience with Python or similar programming or scripting languages for test automation and data analysis.
Strong written and verbal communication skills, including the ability to explain complex technical subjects to engineering teams, senior leadership, customers, and partners.
Ability to provide technical leadership across programs, engineering teams, and technology areas, and to guide and develop other engineers.

Nice To Haves

Master's degree.
PCIe Gen5/Gen6 electrical validation and compliance experience.
Experience with 100G/200G/400G/800G Ethernet.
Advanced SerDes characterization experience.
PAM4 and NRZ signaling experience.
Eye-diagram, jitter, BER, bathtub-curve, and link-margin analysis experience.
S-parameter and VNA-based channel characterization experience.
TDR/TDT and impedance characterization experience.
High-speed PCB and connector characterization experience.
Power-integrity and PDN simulation/measurement correlation experience.
High-current CPU, GPU, ASIC, FPGA, and accelerator power-delivery experience.
Protocol and link-layer debugging experience.
Python-based laboratory automation and data analytics experience.
Experience with server, networking, storage, AI/ML, or high-performance computing platforms.
Experience developing and qualifying complex multi-board systems.

Responsibilities

Serve as the primary technical authority for hardware validation, signal integrity, and power integrity.
Define global validation strategies, establish engineering standards, and influence early product architecture to mitigate system-level risks.
Lead schematic and PCB reviews and improve laboratory infrastructure and simulation-to-measurement correlation.
Direct signal-integrity characterization for advanced interconnects, including PCIe Gen5/Gen6 and 100G–800G Ethernet.
Perform advanced eye-diagram, jitter, and channel-loss testing for NRZ and PAM4 signaling using VNAs, TDRs, and oscilloscopes.
Lead power delivery network validation for high-performance CPU, GPU, and ASIC workloads.
Characterize transient response, ripple, and rail stability, evaluating interactions between power integrity, signal integrity, and thermal behavior.
Drive structured root-cause investigations for complex hardware, firmware, and system-level failures.
Partner with cross-functional and supplier teams to isolate faults and resolve critical customer escalations.
Develop scalable Python-based test automation frameworks for instrumentation control and data acquisition.
Standardize validation infrastructure to improve engineering productivity and enable data-driven decisions.
Mentor senior engineers and guide cross-functional teams through product milestones while aligning technical priorities.
Build strategic relationships with vendors and partners, define future validation roadmaps, and promote engineering rigor.
Set technical direction, identify cross-program risks, and establish scalable solutions.
Influence architecture-level decisions using measurement, analysis, and engineering judgment.
Lead complex technical initiatives spanning multiple engineering disciplines and organizations.
Serve as an escalation point for difficult signal-integrity, power-integrity, high-speed-interface, and system-level hardware problems.
Communicate complex technical topics to customers and senior technical stakeholders.
Translate emerging technologies and customer requirements into validation capabilities and engineering roadmaps.
Balance immediate product execution with longer-term improvements in engineering methodology, automation, laboratory capability, and technical expertise.