Staff Engineer, Physical Design

Marvell Technology•Santa Clara, CA

1d•$111,070 - $166,400

About The Position

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications. You will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. You will be responsible for maintaining, enhancing, and supporting Marvell's Place and Route Flow, leveraging industry-standard EDA tools. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience or equivalent professional experience in lieu of a formal degree
5+ years of experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e.g., 7nm, 5nm, or below) preferred
Proficient with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys IC Compiler and Fusion Compiler
Strong expertise in static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail
Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous
Demonstrated ability to create scripts (Tcl, Perl, Makefile) for automating design processes and improving overall workflow efficiency
Detail-oriented, self-motivated team player with effective communication skills and a commitment to collaborative success

Responsibilities

Maintaining, enhancing, and supporting Marvell's Place and Route Flow, leveraging industry-standard EDA tools.
Performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks.
Developing and implementing timing and logic ECOs.
Collaborating closely with the RTL design team to drive modifications that address congestion and timing issues.
Debugging and resolving any block-level timing issues encountered at the partition level.