Staff Engineer, PCIe PHY/Link Analysis

Samsung Semiconductor•San Jose, CA

3d•Onsite

About The Position

At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures. We are looking for a dynamic, self-motivated engineer to develop and support our cutting-edge Enterprise and Data Center SSD products. The ideal candidate will possess comprehensive expertise across the full PCIe protocol stack - from the Physical Layer (PHY) through the Data Link Layer and up to the Transaction/Transport Layer - with a proven track record in hardware/firmware design, protocol implementation, and complex link bring-up and debugging. This position is based in San Jose, California.

Requirements

BS in Computer/Electrical/Electronic Engineering or Computer Science, and 8+ years of relevant experience in hardware or a MS in Computer/Electrical/Electronic Engineering or Computer Science with 5+ years of relevant experience is required.
Deep proficiency with the PCIe protocol spanning the entire architecture from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer.
Strong hands-on knowledge of LTSSM, link training/equalization, PCIe enumeration, flow control, replay/retry, and error handling (AER).
Working knowledge of PHY-layer operation (CDR to Equalizer such as VGA, CTLE, DFE, FFE, DSP, etc ) sufficient to root-cause link issues that cross the PHY/Link boundary.
Solid experience in C/C++ for embedded systems, and expertise with UART/JTAG/ICE debuggers and general firmware debugging techniques.
Strong experience with PCIe protocol analyzers, logic analyzers, and signal analyzers for link and transaction-level debug.
Ability to work effectively within a multi-functional team environment.

Nice To Haves

Knowledge on SI/PI for PCIe Extended Protocols
Proficiency in NVMe, CXL, or SAS/SATA protocols is a significant plus.
Experience in both pre-silicon and post-silicon SoC validation.
Experience with PCIe power management (ASPM, L1 substates) and low-power link states.

Responsibilities

Understand PHY/Link architecture, implementation, and integration of the PCIe protocol stack from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer, in collaboration with internal H/W teams and external vendors.
Own LTSSM behavior, link training and equalization sequencing, PCIe enumeration, and configuration-space flows during device bring-up.
Analyze and validate TLP/DLLP handling, flow control, credit management, ordering rules, ACK/NAK and replay, error handling (AER), and end-to-end data integrity across the stack.
Analyze and debug complex PHY, Link, and Transport layer issues during bring-up and sustaining stages of NVMe SSD products, from Gen1 to the latest generation (Gen7), covering protocol (LTSSM / PCIe enumeration) and PCIe feature-related issues.
Participate in and support industry PHY/Link compliance tests, including PCI-SIG events.
Provide onsite support for PHY/Link related tasks at customer sites and labs.