Staff Engineer – Microelectronics Packaging Technology
About The Position
As a Staff Engineer – Microelectronics Packaging Technology, you will be part of a multidisciplinary advanced technology team developing highly integrated System-In-Packages (SiP) and module sub-systems for Aerospace, Defense, Industrial, medical use cases. You will be an individual contributor with subject matter expertise to design and layout heterogeneously integrated SiP packages, analyze thermal and mechanical behavior, and support development of SiP design infrastructure. This is an excellent opportunity to work across full spectrum of technology development cycle from conceptualization (early TRLs) to manufacturing readiness (mid-MRLs). This role calls for an individual to provide in-depth engineering analysis, model-based engineering problem solving, and collaborate cross-functionally. You will interface closely with teams across internal manufacturing, operations, business units, external material suppliers, and process vendors. The successful candidate will foster technology-driven thinking for differentiation, but manufacturing-informed for design packaging solutions.
Requirements
- Must possess a strong knowledge across broad spectrum of packaging technology landscape from component packaging to heterogeneously integrated SiPs.
- Must possess good understanding in various packaging elements such as substrate technologies, silicon interconnects, and metallurgy, underfills, epoxies, thermal interface materials, isolating shielding, assembly processes.
- Demonstrate strong understanding in the interdisciplinary nature of packaging by articulating packaging materials behaviors as related to their mechanical, thermal, electrical characteristics, and manufacturability.
- Must have advanced skills in 3D modeling (e.g., SOLIDWORKS) and FEA-based analysis (e.g., ANSYS) for mechanical and thermals. Exposure to basic vibration analysis concepts will be an added advantage.
- Demonstrate ability to optimize package designs and resolve design issues using structured problem-solving techniques based on physics (mathematical models) and/or statistics (DOEs).
- Make balanced engineering decisions for ambiguous problems using structured tradeoff analysis that related to objective goals.
- Ability to collate information with appropriate supporting data and present into a coherent report for communication and distribution.
- Bachelor’s degree in mechanical engineering, that includes material’s coursework.
- Minimum 9+ Years Relevant Experience
- 6 to 7 years of hands-on semiconductor packaging development experience
- Must have a background that would permit the U.S. Department of Defense to issue a Secret clearance when necessary for work on a project that requires such a clearance.
- Must comply with TTM Export Control Policies and Procedures and all applicable laws including ITAR, EAR and OFAC including but not limited to: a) being able to identify ITAR product on the manufacturing floor and understand that access to these products and related technical data is restricted to only US Citizens and US Permanent Residents; b) recognition of Foreign Person visitors by badge differentiation; c) understand and follow authorization procedures for bringing foreign visitors into facilities (VAL); d) understand the Export and ITAR requirements for shipments leaving the US; e) manage vendor approvals for ITAR manufacturing and services.
Nice To Haves
- Master’s education will be a plus
- Exposure to basic vibration analysis concepts will be an added advantage.
Responsibilities
- Lead the design and development of advanced SiPs and module package solutions using 2D/3D packaging technologies with 50micron to 130micron flip-chip interconnects, WLP bumped die, and embedded die.
- Provide technical leadership in support of package architecture selection by generating 3D package designs, manufacturability, and risk assessments.
- Generate and optimize detailed package designs in 3D environment using SOLIDWORKS. This will be done in collaborate with RF/MW/electrical engineering teams
- Perform complex physics-based mechanical and vibration simulations for SiP configurations using FEM tools (ANSYS) to analyze chip-package interaction, package-board interaction, warpage, stress, and reliability risks.
- Perform SiP-level thermal simulations for microelectronics packages using FEM tools (ANSYS)
- Define and assist in the buildup of SiP design infrastructure that includes package design flows, 3D modeling and simulation methodologies, generating package design rules.
- Lead or assist in writing white papers, technical proposals, and conference publications.
- Benchmark industry best practices and evaluate emerging technologies for package design, assembly materials, and process innovations.
- Perform and collate tradeoff analysis on ambiguous problems that considers interdisciplinary nature of semiconductor packages.
- Communicate complex technical concepts effectively to cross-functional project teams, operations, suppliers, business teams
- Be creative in designing and developing innovative integration methods that foster the spirit of differentiation and generation of IPs
- Assist in project management by providing planning inputs for defining packaging tasks, schedule, and cost.
Benefits
- medical
- dental
- vision
- 401k
- flexible spending and health savings accounts
- accident benefits
- life insurance
- disability benefits
- paid vacation & holidays
- An annual or quarterly company bonus may apply based on position assignment.
- Positions hired for alternative shift may be eligible for a shift premium based on the assigned shift and location.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
