Power Analysis

Marvell Technology•San Diego, CA

2d•$115,200 - $170,390

About The Position

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOC) to systems of chips. In the era of Accelerated Computing, data bottlenecks are no longer limited to compute performance, but rather the system interconnect bandwidth, memory bandwidth, and memory capacity. Marvell's Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions. The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies. This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Marvell is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers. We are seeking a highly skilled and experienced Timing/STA Engineer to join our team. The ideal candidate will have a strong background in timing constraints development, STA Signoff/Margins flows & methodologies for both SOC level and block level. They should have experience that includes running STA signoff flows, understanding of STA signoff margins, generating timing ecos, developing timing constraints, timing budgeting, optimization and timing closure of high-speed designs. Additionally, experience with deep technology nodes such as 5nm/4nm would be valued.

Requirements

Minimum of 1 year of industry experience in ASIC timing and STA.
Strong understanding of ASIC design flows, from RTL to GDSII.
Knowledge and hands-on experience with STA methodologies and implementation.
Proficiency in using STA tools, and scripting languages (e.g., Tcl, Perl).
Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5.
Strong understanding of timing constraint development for hierarchical designs, timing ECO creation and final timing signoff.
Familiarity with physical design and timing optimization techniques and strategies to achieve deterministic timing closure.
Proven track record of delivering successful designs on time and meeting performance, power and area goals.
Excellent problem-solving skills, attention to detail, and ability to analyze and debug complex issues.
Strong communication and collaboration skills to work effectively within cross-functional teams.

Nice To Haves

Experience with deep technology nodes such as 5nm/4nm.

Responsibilities

Develop and validate timing constraints for intricate SoC designs.
Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for sta signoff.
Own and contribute to various sta related tasks like doing timing ecos for blocks and SoCs, developing custom scripts to create histograms, sta flow management, etc.
Perform static timing analysis (STA) using industry-standard tools (e.g. Primetime).
Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
Resolve or find workarounds for tool issues, independently or working with EDA tool vendors.
Conduct post-route timing checks and quality of results (QoR) analysis.
Automate STA related processes/flow using scripting languages such as Tcl or Python.
Create QoR dashboards, histograms for STA runs across all modes.
Ensure compliance with timing signoff checklists and criteria.
Document best practices and lessons learned to drive continuous improvements in future projects.