Senior ASIC Implementation Engineer, Low Power AI

Qualcomm • Markham, ON

1d • CA$115,600 - CA$165,600

About The Position

Qualcomm Technologies Audio products are designed to offer premium wireless connectivity, high levels of integration, immersive sound quality, and on-device AI for smart audio and context aware applications. An ultra-low power subsystem within a low power SoC; a chip-within-a-chip HW block incorporating multiple always-on IP's, design execution within this group requires solving ground-breaking challenges and multiple power domain crossing issues. As we are pioneer new and/or improved functionality, innovate to minimize power consumption. Make a difference, join a team on the cutting edge and become an integral part of Qualcomm’s growth and momentum. We are looking for an ASIC Implementation Engineer to be part of our team to innovate and design complex leading, ultra-low power, solutions for audio and context aware applications. We are open to all levels of applicants, with responsibility being commensurate with experience. We are looking for applicants who thrive when presented with constant opportunities for learning and growth and who want to have a large impact on our team. New Position

Requirements

• 2 years of professional ASIC hardware design and/or implementation experience.
• Expertise with Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL.
• Exceptional understanding of ASIC/VLSI concepts
• Experience in logic synthesis using Synopsis and/or Cadence tools.
• Detail oriented with strong analytical and debugging skills
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ years of ASIC design, verification, or related work experience.
• PhD in Science, Engineering, or related field.

Nice To Haves

• Strong communication (written and verbal) and collaboration skills
• Working knowledge of UPF specification
• Experience with synthesis, STA
• Experience with High-speed/Low power ASIC design within a Unix environment
• Experience with clock domain crossing techniques and tools
• Scripting skills (Python , PERL, TCL or C)

Responsibilities

• Synthesis
• Timing Constraints
• Implementing ECOs
• STA
• Power intent validation (CLP)
• Lint
• Power Analysis Tasks
• CDC validation
• Model and analyze performance, area, power, and system cost tradeoffs for different micro-architectures
• Contribute to implementation methodologies/ flows
• CLP (RTL and/or netlist)
• PTPX / power pro
• Power analysis / optimization
• ASIC design tasks including some RTL development

Benefits

• competitive annual discretionary bonus program
• opportunity for annual RSU grants
• highly competitive benefits package is designed to support your success at work, at home, and at play

What This Job Offers

• Job Type: Full-time
• Career Level: Senior