Staff DV Engineer

E-Space•Saratoga, CA

6d•Onsite

About The Position

E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony.

Requirements

Strong proficiency in Verilog and SystemVerilog.
Experience writing tests within an existing UVM verification environment.
Solid understanding of UVM architecture and methodology.
Ability to write C/C++ code for verification purposes.
Some scripting experience in Perl or Python.
Ability to contribute to and help write test plans.
Experience writing and maintaining verification tests.
Ability to debug RTL simulations independently.
Experience leading design verification efforts at the block level.
Experience driving code coverage closure on assigned blocks.
6+ years of design verification experience in the semiconductor industry.
Passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities.
Work authorization for the location of this role.