Principal DV Engineer

E-Space • Saratoga, CA

7d • Onsite

About The Position

E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. We prioritize AI assistance to accelerate work.

Requirements

• Expert-level proficiency in Verilog and SystemVerilog
• Proven experience building UVM verification environments from scratch
• Deep understanding of verification methodologies and best practices
• Proficient in C/C++ coding for verification purposes
• Strong scripting skills in Perl or Python
• Ability to write and maintain bash scripts for verification flows
• 10+ years of design verification experience in the semiconductor industry
• Passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities.

Nice To Haves

• VHDL is valuable.

Responsibilities

• Verify custom ASICs for satellite and wireless telephony.
• Lead code coverage closure.
• Lead design verification efforts through chip tapeout.
• Write comprehensive test plans.
• Write and maintain test suites.
• Debug complex RTL simulations.
• Debug gate-level simulations with SDF back-annotation.
• Assess whether SDF timing violations are benign or require attention.

Benefits

• Competitive salaries
• Continuous learning and development
• Health and wellness care options
• Financial solutions for the future
• Optional legal services (US only)
• Paid holidays
• Paid time off

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: No Education Listed