Staff DFT Engineer

Marvell Technology • Burlington, VT

8d

About The Position

The Custom Silicon team in Marvell designs and develops complex, high-speed, high-performance custom chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure. The Design-for-Test (DFT) team is a global team that impacts chip design from inception all the way to manufacturing production. Rigorous DFT methods ensure that a part can be tested with an extremely high degree of defect coverage in a time-constrained manufacturing environment, directly impacting product quality and customer satisfaction. The ideal candidate will possess both digital logic design and verification skills along with software development and programming skills. Such a candidate will enjoy an opportunity that spans disciplines and involves them in all aspects of semiconductor chip design.

Requirements

• Bachelor of Science degree in Computer or Electrical Engineering with at least 3-5 years of related professional experience, or Master of Science degree in Computer or Electrical Engineering with at least 2-3 years of related professional experience, or PhD in Computer or Electrical Engineering
• Digital logic design skills with Verilog
• Hands-on experience with scan-based logic test, memory BIST/BISR, functional test, JTAG, and other test methodologies
• Experience with EDA DFT tools (Siemens EDA Tessent, Cadence Modus, or Synopsys TestMAX)
• Demonstrable programming skills with TCL, Python, Perl, or csh/bash in Unix type environment, with good problem-solving skills
• Good understanding of Linux/Unix, with experience working on distributed systems
• Effective teamwork and communication skills

Responsibilities

• Develop understanding of both the block level and chip top design-for-test (DFT) and automated test pattern generation (ATPG) flows for complex custom silicon designs
• Execute DFT insertion and verification flows for scan test, Memory Built-in Self-Test (MBIST), and IP macro test
• Execute digital logic, MBIST, and IP test pattern generation and simulation flows
• Analyze results and look for ways to improve test coverage
• Collaborate with the global DFT team on design flow improvements
• Support manufacturing test hardware bring-up and pattern debug

Benefits

• employee stock purchase plan with a 2-year look back
• family support programs to help balance work and home life
• robust mental health resources to prioritize emotional well-being
• recognition and service awards to celebrate contributions and milestones

What This Job Offers

• Job Type: Full-time
• Career Level: Senior