Sr Staff SoC Design Verification Manager

Marvell Technology•San Diego, CA

About The Position

Join Marvell's Custom Compute Solutions Business Unit (CCSBU) as we establish our design presence in San Diego's thriving semiconductor ecosystem. This team will be responsible for delivering high‑quality customer silicon for advanced AI, XPU, and XPU‑Attach programs. By partnering closely with customers and internal stakeholders, the design center will enable Marvell’s most strategic and financially significant custom SoC initiatives, delivering differentiated solutions that reinforce Marvell’s position as a trusted partner for next‑generation compute platforms. This is a rare foundational lead opportunity - you'll help shape design strategy from the ground up and help build a world-class team as part of our strategic expansion into Southern California. You're not joining an established local team - you're contributing to building one. You'll define the culture, establish the methodology, and shape the technical DNA of Marvell's San Diego design verification organization.

Requirements

BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 8+ years experience).
5+ years of experience leading a design verification team.
Experience with SystemVerilog, UVM.
Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.
Experience with scripting language such as Python or Perl and EDA Verification tools.
Experience with Object-Oriented Design and implementation.
Good understanding of Linux O.S.
Good programming skills desired, especially C++ and ARM assembly.
Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.
Requires the ability to accept and work with differing opinions.
Cannot be a close-minded developer.
Must be able to learn on the fly and work in a fast-paced environment.

Nice To Haves

Understanding of networking protocols, a plus.

Responsibilities

Lead DV, emulation and post silicon validation execution with zero defect mindset.
Define DV, emulation and post silicon validation scope.
Define execution timelines working closely with stakeholders.
Set goals, monitor, and take steps to keep the execution on track.
Define DV methodology and verification strategies.
Drive definition and implementation of DV TB architectures.
Collaborate with Architecture, Design, DFT, PD, FW and system teams for successful product execution.
Lead tool evaluation and selection.
Drive continuous productivity improvements through incremental and forklift changes.
Monitoring industry DV trends and adapting to key trends.
Hire, build and retain high performance engineering team.
Address continuous training and development needs of the team.