Sr. Staff Packaging Engineer- Process Package Integrity & Bumping

Qualcomm•San Diego, CA

13d•$191,800 - $287,800

About The Position

The engineer will be a key member of the Process Package Integration and bumping process team, driving technology development and new product introduction (NPI) with primary ownership of wafer bumping (Far-BEOL) process integration, qualification, and high-volume readiness across multiple silicon technology nodes, foundries, bumping lines, and assembly houses (OSATs). Key responsibilities include defining bumping process flows (passivation/UBM/RDL/bump), establishing process windows and controls, leading DOE-based optimization, and partnering with suppliers to improve yield, reliability, and cost. The role works closely with foundry FBEOL teams, bumping/assembly partners, and internal package design, process, quality, test, and product development teams to deliver robust bumping solutions enabling advanced packaging (flip-chip, RDL/fan-out, and 2.5D/3DIC). The candidate will also lead bumping house/line bring-up, qualification, and ongoing performance management to expand capacity and ensure multi-source readiness.

Requirements

Expertise in Far-BEOL bumping process modules and integration, including passivation openings, UBM, RDL (as applicable), solder/Cu pillar bump formation, and associated materials/equipment.
Deep knowledge of flip-chip bump design intent and assembly interactions (bump metallurgy, pitch scaling, coplanarity, warpage interactions), and wafer-level packaging (RDL) / fan-out process considerations impacting bumping.
Strong technical skills in bumping process/material/equipment characterization (metrology and inline controls), failure analysis, DOE design, statistical data analysis, and FMEA to drive yield and reliability improvements.
Experience leading bumping process qualification and production release activities (process window definition, control plans/SPC, GR&R, and risk mitigation) for NPI and high-volume manufacturing.
Proven track record enabling package development through robust bumping solutions for flip-chip, RDL/fan-out RDL, and advanced packaging technologies (2.5D/3DIC).
Expertise in manufacturing execution for Far-BEOL bump structures and bump line operations, including new bumping line bring-up, tooling/equipment qualification, and production ramp (HVM readiness).
Hands-on experience in project leadership and supplier management for external bumping houses/OSATs
Experienced interfacing with foundries and bumping houses on process integration, change control, line qualification, and multi-source/capacity expansion.
Understanding of heterogeneous integration (2.5D/3DIC) packaging flows and how bumping/interconnect schemes (micro-bumps, fine-pitch RDL) impact downstream assembly and reliability.
Experience with chip and substrate design tools such as Calibre, Virtuoso, CAD, SiP, and GDS.
Understanding of chip-top physical design flow and communication with package design teams.
Minimum of 8–10 years hands-on experience in silicon interconnect process, bumping and/or RDL process, new technology qualification and production.
Good analytical and project management skills.
Excellent capability of innovation and creativity.
Highly motivated and committed to success of the individual and the team.
Superior interpersonal communication skills.
Able to work flexible hours.
Occasional domestic/international travels needed.
Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 6+ years of System/Package Design/Technology Engineering or related work experience.
OR Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 5+ years of System/Package Design/Technology Engineering or related work experience.
OR PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ year of System/Package Design/Technology Engineering or related work experience.

Responsibilities

Defining bumping process flows (passivation/UBM/RDL/bump)
Establishing process windows and controls
Leading DOE-based optimization
Partnering with suppliers to improve yield, reliability, and cost
Working closely with foundry FBEOL teams, bumping/assembly partners, and internal package design, process, quality, test, and product development teams to deliver robust bumping solutions enabling advanced packaging (flip-chip, RDL/fan-out, and 2.5D/3DIC)
Leading bumping house/line bring-up, qualification, and ongoing performance management to expand capacity and ensure multi-source readiness
Defining KPI's for external bumping houses/OSATs
Containing yield excursions
Implementing continuous improvement programs
Interfacing with foundries and bumping houses on process integration, change control, line qualification, and multi-source/capacity expansion
Designing and driving novel test vehicles/structures for bump/RDL process characterization and process-package interaction (reliability, electromigration, mechanical integrity)