Sr Staff Engineer, Program/Project Management- Test Readiness Lead

Celestica•Austin, TX

23h

About The Position

The Senior Manager of HPS Test Engineering owns end-to-end testing architecture, strategy, and execution for next-generation products and infrastructure. The position connects silicon designers, internal hardware and software teams, and volume manufacturing operations, and leads a team of test hardware and software engineers developing solutions such as ICT, FCT, SLT, BI, and Boundary Scan. The role works cross-functionally with the Front-End Senior Manager, Back-End Senior Manager, and Director of Technology Roadmapping to maximize test coverage, reduce escapes, and optimize manufacturing throughput and first-pass yield. The position manages and develops the test engineering team, sets metrics and deliverables, and coordinates engineering resources, capital equipment budgets, and lab infrastructure across NPI initiatives. It leads early design-for-testability reviews and silicon-provider collaboration, and defines product test specifications, coverage matrices, test-point allocations, and optimization bounds before design freeze. The role oversees test solution architecture and deployment across multiple test stages, analyzes production data to improve yield and test stability, and provides hands-on guidance for prototype bring-up, debugging, fixture qualification, diagnostic software checks, and test-binary version control. Duties are performed in a normal office environment and may require occasional travel.

Requirements

At least 5 years of direct experience leading and scaling multidisciplinary test hardware and software engineering teams.
At least 8 years of engineering experience in test development, functional testing architecture, ATE hardware infrastructure, or NPI test leadership in high-density hardware industries.
Proven experience deploying complex test vectors for high-speed digital systems, enterprise servers, or hyperscaler infrastructure, or working directly with tier-1 silicon providers.
Expert understanding of DFT methodologies and IEEE 1149.x Boundary Scan (JTAG).
Expertise with high-speed serial links, including PCIe Gen 5/6 and SerDes.
Expertise in instrumentation automation and programming frameworks such as Python, C/C++, and LabVIEW.
Experience with database/data-mining systems for statistical process control (SPC).
Outstanding project management maturity and metrics-driven problem-solving skills.
Ability to translate technical yield constraints into business risks for executive and customer reviews.
Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline; educational requirements may vary by geography.

Nice To Haves

Six Sigma Black Belt.

Responsibilities

Directly manage, coach, and mentor test hardware and software engineers.
Define test engineering metrics, KPIs, and deliverables; conduct performance evaluations and outline engineering career paths.
Plan and manage engineering bandwidth, test equipment capital budgets, and lab infrastructure across concurrent NPI initiatives.
Lead design-for-testability and design-for-excellence reviews during schematic and board-layout stages.
Collaborate with silicon partners on built-in self-test, high-speed JTAG boundary scan architectures, and custom diagnostic hooks.
Develop unified product test specifications, coverage matrices, test-point allocations, and optimization bounds before design freeze.
Oversee the specification, architecture, and deployment of ICT, FCT, SLT, and environmental stress screening/burn-in solutions.
Analyze production data to identify false failures, test instability, and gauge R&R shortfalls, and optimize test limits and fixture designs.
Guide initial test vehicle bring-up and debugging, fixture qualification, diagnostic software stability checks, and test-binary version control.
Maintain cross-functional alignment with front-end and back-end senior managers and technology roadmapping leadership.