Sr Staff Engineer, Program/Project Management- Test Readiness Lead

Celestica International LP•Austin, TX

About The Position

The role leads end-to-end test architecture, strategy, and execution for next-generation products and infrastructure. It connects silicon designers, internal hardware and software teams, and volume manufacturing operations, while leading a team of test hardware and software engineers developing test solutions including ICT, FCT, SLT, BI, and Boundary Scan. The role maintains cross-functional alignment with the Front-End Senior Manager, Back-End Senior Manager, and Director of Technology Roadmapping to maximize test coverage, minimize escapes, and optimize manufacturing throughput and first-pass yield. Responsibilities include managing and developing a specialized engineering team; setting metrics and performance expectations; allocating engineering capacity, test equipment budgets, and lab resources across NPI initiatives; leading DFT/DFx reviews during schematic and board-layout design; collaborating with silicon partners on BIST, JTAG boundary scan, and diagnostic hooks; and defining product test specifications and coverage plans before design freeze. The role also oversees the architecture and deployment of ICT, FCT, SLT, and environmental stress screening/burn-in solutions. It analyzes production data to identify false failures, test instability, and gauge R&R issues, and guides initial test vehicle bring-up, debugging, fixture qualification, diagnostic software checks, and test-binary version control. Duties are performed in a normal office environment and may involve occasional travel.

Requirements

5+ years of direct experience leading and scaling multidisciplinary test hardware and software engineering teams.
8+ years of dedicated engineering experience in test development, functional testing architecture, ATE hardware infrastructure, or NPI test leadership in high-density hardware industries.
Expert-level understanding of DFT methodologies and IEEE 1149.x Boundary Scan (JTAG).
Expertise in high-speed serial links, including PCIe Gen 5/6 and SerDes.
Expertise in instrumentation automation and programming frameworks such as Python, C/C++, and LabVIEW.
Expertise with database/data-mining systems for statistical process control (SPC).
Outstanding project management maturity and metrics-driven problem-solving ability.
Ability to translate technical yield constraints into business risks for C-suite and customer reviews.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline; educational requirements may vary by geography.

Nice To Haves

Six Sigma Black Belt preferred.
Experience deploying complex test vectors for high-speed digital systems, enterprise servers, or hyperscaler infrastructure.
Experience working directly alongside tier-1 silicon providers such as Nvidia, Broadcom, or Marvell.

Responsibilities

Directly manage, coach, and mentor test hardware and software engineers.
Define test engineering metrics, KPIs, and deliverables; conduct performance evaluations and establish engineering career paths.
Plan engineering bandwidth, test equipment CapEx budgets, and lab infrastructure allocations across concurrent NPI initiatives.
Lead DFT/DFx technical reviews during early schematic and board-layout design to maximize test access.
Collaborate with silicon architects to incorporate BIST, high-speed JTAG boundary scan, and custom diagnostic hooks.
Develop unified product test specifications, including test coverage matrices, test-point allocations, and optimization bounds before design freeze.
Oversee specifications, architecture, and deployment of ICT, FCT, SLT, and ESS/burn-in solutions.
Analyze production data to identify false failures, test instability, and gauge R&R shortfalls; optimize test limits and fixture designs.
Guide initial test vehicle bring-up and debugging, test fixture qualification, diagnostic software stability checks, and test-binary version control.
Maintain cross-functional alignment with the Front-End Senior Manager, Back-End Senior Manager, and Director of Technology Roadmapping.
Occasional travel may be required.