Sr. Staff Engineer, ASIC Verification - AI/HPC SOCs

Marvell Technology•Toronto, ON

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. This is an existing vacancy. Your Team, Your Impact Custom Silicon Engineering (CSE) group is part of Data Center Engineering (DCE) Business Unit, closely collaborates with strategic Hyper scalar and Data Center customers in the development of advanced and highly complex custom SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. What You Can Expect . Work on verification of memory, AI/HPC or Die-2-Die subsystems of Marvell's AI/ML, Network processing, Compute, Memory Expander and Accelerated Compute SOCs and IPs. Contribute to the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology. Contribute to or develop test strategies that will ensure functional correctness. Develop verification testplan and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete. Debug failures and work with designers to resolve issues. Contribute to the development and future direction of SoC verification methodologies and environments.

Requirements

Bachelor’s degree in Electrical engineering, Electronics, Computer engineering, or related fields with 10+ years of experience.
Master’s degree and/or PhD in Electrical engineering, Electronics, Computer engineering, or related fields with 8+ years of experience.
8+ years of experience in design engineering with focus on verification.
At least 5 years of direct hands-on verification experience on PCIe, NOC, DDR, HBM, Processor cores or AI or HPC accelerators at block, subsystem and full chip level contexts.
Strong experience developing complex/random verification environments using System Verilog/UVM
Strong experience with writing and executing detailed verification test-plan.
Strong experience with scripting languages such as Python or Perl and EDA verification tools, as well as bug tracking and regression mechanisms.
Strong experience with object-oriented design and implementation.
Excellent communication skills to interface internally and externally with all levels of the organization and to participate in problem-solving and quality improvement activities.
Demonstrates good analytical and problem-solving skills.
Must have the ability to define problems, issues, and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.
Must have the ability to multi-task in a fast-paced environment.

Responsibilities

Work on verification of memory, AI/HPC or Die-2-Die subsystems of Marvell's AI/ML, Network processing, Compute, Memory Expander and Accelerated Compute SOCs and IPs.
Contribute to the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology.
Contribute to or develop test strategies that will ensure functional correctness.
Develop verification testplan and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete.
Debug failures and work with designers to resolve issues.
Contribute to the development and future direction of SoC verification methodologies and environments.