Sr Staff Applications Engineer, HAV Solutions

Synopsys•Sunnyvale, CA

55d•$157,000 - $235,000•Remote

About The Position

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You have spent years moving between RTL, FPGAs, and real hardware, and you know that the gap between a design that compiles and one that actually boots is where most projects stall. You understand partitioning tradeoffs, clock domain crossings, and why a PCIe link trains in simulation but fails on the board. You have debugged DDR timing issues at 2 a.m., explained why a billion-gate SoC will not fit without rearchitecture, and walked a customer through a critical bring-up when everything seemed broken. You do not just run tools. You understand what ProtoCompiler is doing under the hood, why timing closed on FPGA A but not FPGA B, and how to instrument a design for visibility without destroying performance. When a customer escalation lands, you are the person who can reproduce it, explain it to R&D, and propose a workaround that actually works in production. You have worked with hyperscalers, automotive teams, AI chip startups, or aerospace groups building systems too complex to simulate. You speak their language. You know the difference between emulation and prototyping, and you can articulate when each makes sense without sounding like a sales pitch. At Synopsys, you will work on the hardest prototyping problems in the industry with customers who are building the next generation of AI, automotive, and datacenter silicon.

Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands-on experience
10+ years working in FPGA implementation, ASIC design, ASIC verification, hardware-assisted verification, FPGA prototyping, or emulation
Deep expertise in FPGA synthesis, place-and-route, multi-FPGA partitioning, timing closure, and constraint development using Xilinx Vivado, Intel Quartus, or equivalent tools
Strong working knowledge of SystemVerilog, UVM, assertions, functional coverage, and verification testbench architecture
Hands-on experience with interface IP including PCIe, DDR4/DDR5, LPDDR, Ethernet, USB, AXI, CXL, or high-speed SerDes protocols
Proficiency in Tcl, Python, or shell scripting for automation and flow development
Direct experience with Synopsys HAPS and ProtoCompiler is a strong plus, as is experience with ZeBu, Palladium, Protium, or Veloce emulation platforms

Nice To Haves

You can walk into a room with a customer's architecture team, understand their SoC in an hour, and identify the three partitioning decisions that will make or break their prototype schedule
When a PCIe link will not train or a DDR interface fails calibration, you know where to look first and how to instrument the design to prove your hypothesis
You are comfortable presenting technical tradeoffs to VPs and engineering directors without oversimplifying the problem or losing the nuance that matters
You do not wait for perfect information or complete documentation. You dig into logs, RTL, netlists, and hardware captures to figure out what is actually happening
You have debugged designs using Verdi, runtime instrumentation, protocol analyzers, or assertion-based techniques and can teach others how to do the same
You can explain why emulation and prototyping solve different problems, and you have the technical depth to back up that explanation with real architectural tradeoffs

Responsibilities

Lead technical deployments of HAPS-200 and ProtoCompiler for strategic customers building billion-gate SoCs across AI/ML, automotive, hyperscaler, and aerospace segments
Drive the full ASIC-to-FPGA flow including partitioning, clock conversion, synthesis, place-and-route, timing closure, bitstream generation, and hardware bring-up on multi-FPGA systems
Debug complex interface IP subsystems including DDR4/DDR5, LPDDR5/6/7, HBM, PCIe Gen3-6, CXL, UCIe, Ethernet, USB, AXI, and high-speed SerDes architectures
Reproduce, analyze, and resolve critical customer escalations involving RTL issues, partitioning failures, timing violations, protocol mismatches, and hardware bring-up failures
Collaborate directly with ProtoCompiler R&D and Product Management to validate new features, influence roadmap priorities, and represent customer requirements in product planning
Develop and document reusable methodologies for partitioning strategies, clock architecture, debug instrumentation, verification environment adaptation, and hardware/software co-validation
Mentor applications engineers globally, lead technical workshops and architecture reviews, and represent Synopsys at customer sites, conferences, and industry forums