Sr. RTL Design Engineer (Silicon Engineering)

SpaceX•Redmond, WA

2h•$160,000 - $225,000

About The Position

SpaceX is seeking a motivated, proactive, and intellectually curious engineer to work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

Requirements

Bachelor’s degree in electrical engineering, computer engineering, or computer science
5+ years of experience in RTL implementation

Nice To Haves

Ability to solve complex problems including clock domain crossings and power optimization
ASIC/SoC system integration experience
Experience with embedded CPU subsystems
Experience with standard bus protocols (e.g. AXI, AHB, etc.)
Experience with high speed and low power design techniques
Scripting skills (e.g. Python, etc.)
Experience with EDA tools such as HDL simulators and HDL Lint tools
Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
Enjoys being challenged and learning new skills

Responsibilities

Evaluate architectural trade-offs based on features, performance requirements and system limitations
Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
Work closely with verification team to ensure all aspects of the design are covered and verified
Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
Participate in silicon bring-up and validation