Sr. Principal Foundry Interface Engineer

SiTime Corporation•Santa Clara, CA

About The Position

In this role, the candidate will support Foundry technical interface for SiTime. The key responsibilities include the following. It is not necessary to meet all job requirements to be a qualified candidate for the position.

Requirements

Minimum requirements are a Master’s degree with 13+ years of experience or a PhD with 10+ years of industry experience in a relevant engineering or physical-science field, including Semiconductor Process Integration, Device Engineering, or Wafer Yield Engineering.
English proficiency is required, including the ability to effectively communicate, collaborate, and perform job responsibilities in a professional business environment.
Proven track record in yield pareto construction, modeling, projection, and the development of long-term yield roadmaps.
Experience in using PDF Exensio or other Big Data Analysis tools.
Extensive experience collaborating with foundries.
Experience in porting between fabs.
Expertise in interpreting complex product data (inline, e-test, and SORT) to drive organization-wide solutions.
Deep knowledge of semiconductor wafer inline inspection methods and SORT programs.
Deep knowledge of semiconductor device reliability
Well versed with DFM techniques and PFMEA
Experience in supporting semiconductor wafer fulfillment for products that require to meet Automotive AEC_Q100, ISO 26262 standards.
Strong Leadership and ability to set standards and drive to targets.
This position requires clear, accurate and timely communication both written and verbally.
Strong attention to detail, project management and organization skills, and ability to manage multiple projects at the same time in a fast-paced environment with minimal supervision.

Nice To Haves

Experience with AI/ML predictive modeling to improve projection accuracy for test chips and high-volume products, including correlation of inline process metrics with end-of-line yield and performance, is a plus.
Strong team worker within multi-disciplinary and multi-cultural environments.
Show inherent sense of urgency and accountability.
Excellent communication, presentation, interpersonal and team-work skills.
Highly motivated self-starter with a ‘can-do’ attitude, out-of-the-box thinking, with a willingness to take informed risks to achieve organization goals.

Responsibilities

Lead Foundry yield improvement through mitigation of systematic and parametric yield detractors
Manage Foundry yield excursion and implementation of Continuous Improvement Plan.
Manage Foundry safe launch
Provide technical guidance on Foundry Fab transfer projects
During development, direct wafer lot progress, process skew splits and DOE strategies
Support device performance analysis for mixed signal devices.
Manage compliance with fab yield, E-test, WAT, inline Cp/CpK metrics
Serve as technical liaison to the Foundries, communicate status of process health monitors to internal stakeholders, drive on time wafer out from the fab, continuous improvement deliverables and resolution of critical technical escalations.