Principal Foundry Interface Design Engineer, HBM

Micron • Folsom, CA

3d • Onsite

About The Position

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the HBM Design Architecture team within Micron’s HBM DRAM Engineering Group. We work at the intersection of design, technology, and manufacturing to deliver next‑generation HBM solutions that power AI and ML workloads worldwide. Our team thrives on deep technical collaboration, global partnerships, and solving problems that truly push memory technology forward! In this full‑time onsite role, you will provide critical technology support for the design and development of advanced HBM DRAM products. You will serve as a bridge between internal design teams, foundries, and technology development groups, helping translate advanced process capabilities into scalable, high‑performance architectures. Your work will directly impact performance, power efficiency, reliability, and long‑term HBM roadmap success. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. The responsibilities outlined below represent key areas of focus for this role and are intended to be illustrative rather than exhaustive. Candidates are expected to demonstrate relevant experience in at least three of the five focus areas outlined below.

Requirements

• BS, MS, or PhD or equivalent experience in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of semiconductor industry experience, solid grasp of advanced semiconductor technology development.
• Strong understanding of advanced CMOS technology nodes, FinFET devices, and process integration.
• Hands-on experience with: HSPICE simulations, Device characterization, Standard cell benchmarking, PPA analysis, Parasitic extraction and physical verification
• Experience in driving AI-enabled engineering practices and automation to improve the efficiency of DTCO analysis, foundry collateral evaluation, PDK enablement, benchmarking, and knowledge sharing across design teams.

Nice To Haves

• Experience working directly with leading foundries such as TSMC, Samsung, Intel Foundry Services, or GlobalFoundries.
• Experience with memory products including DRAM, HBM, or SRAM.
• Knowledge of: TSV technologies, Advanced packaging, Reliability modeling and aging simulations, Advanced BEOL technologies, PDK development and validation
• Ability to utilize AI tools to summarize, analyze, and extract insights from: PDK documentation, Design Rule Manuals (DRM), Reliability reports, Foundry collateral, Silicon characterization data
• Experience leading technology pathfinding and node selection activities.

Responsibilities

• Act as the primary technical interface between foundry partners and Micron design organizations.
• Drive closure of design-process gaps through collaborative engagement with foundry process teams.
• Influence foundry roadmaps related to TSV, BEOL, reliability, and design enablement.
• Define technology requirements for future HBM and custom memory products.
• Perform HSPICE simulations for technology evaluation and design optimization.
• Evaluate compact models, PDK SPICE models, and process corners.
• Conduct pre-layout and post-layout circuit analysis.
• Support BEOL optimization and routing studies through simulation.
• Develop methodologies for evaluating design sensitivity to process variations.
• Plan and execute technology evaluation test chips.
• Define process monitor structures and benchmark vehicles.
• Analyze post-silicon data and correlate results with simulations.
• Collaborate with product engineering and foundry/Fab teams on silicon learning and technology qualification.
• Evaluate foundry PDKs and IP collateral.
• Support design teams by providing technology guidelines and best-known methods.
• Drive creation of design recommendations, analog guidelines, and digital PPA evaluation methodologies.
• Collaborate with CAD teams on flow enablement and validation.
• Identify and implement AI-enabled workflows, automation opportunities, and knowledge-management practices to improve engineering productivity, decision quality, and execution efficiency across DTCO, foundry interface, PDK evaluation, and design enablement activities.

Benefits

• choice of medical, dental and vision plans
• benefit programs that help protect your income if you are unable to work due to illness or injury
• paid family leave
• robust paid time-off program
• paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Principal