Sr. Principal Engineer, Foundry Interface

SiTime Corporation•Santa Clara, CA

6d•$148,320 - $203,940

About The Position

The Sr. Principal Engineer, Foundry Interface will support SiTime’s technical interface with foundries. The role leads foundry yield improvement by mitigating systematic and parametric yield detractors, managing yield excursions and continuous improvement plans, and overseeing safe launch. It provides technical guidance on foundry fab-transfer projects and, during development, directs wafer-lot progress, process-skew splits, and DOE strategies. The engineer also supports performance analysis for mixed-signal devices and manages compliance with fab yield, E-test, WAT, and inline Cp/CpK metrics. The position serves as a technical liaison to foundries, communicating process-health-monitor status to internal stakeholders, driving timely wafer output, delivering continuous improvements, and resolving critical technical escalations. The role may also use AI/ML predictive modeling to improve projections for test chips and high-volume products by correlating inline process metrics with end-of-line yield and performance.

Requirements

Master’s degree with 13+ years of experience, or PhD with 10+ years of industry experience, in a relevant engineering or physical-science field, including Semiconductor Process Integration, Device Engineering, or Wafer Yield Engineering.
English proficiency, including the ability to communicate, collaborate, and perform job responsibilities effectively in a professional business environment.
Proven track record in yield pareto construction, modeling, projection, and development of long-term yield roadmaps.
Experience using PDF Exensio or other Big Data Analysis tools.
Extensive experience collaborating with foundries.
Experience porting between fabs.
Expertise interpreting complex product data (inline, e-test, and SORT) to drive organization-wide solutions.
Deep knowledge of semiconductor wafer inline inspection methods and SORT programs.
Deep knowledge of semiconductor device reliability.
Knowledge of DFM techniques and PFMEA.
Experience supporting semiconductor wafer fulfillment for products required to meet Automotive AEC_Q100 and ISO 26262 standards.
Strong leadership and ability to set standards and drive to targets.
Clear, accurate, and timely written and verbal communication.
Strong attention to detail, project-management and organization skills, and ability to manage multiple projects in a fast-paced environment with minimal supervision.

Nice To Haves

Experience with AI/ML predictive modeling to improve projection accuracy for test chips and high-volume products, including correlation of inline process metrics with end-of-line yield and performance.
Strong team-worker skills in multidisciplinary and multicultural environments, with an inherent sense of urgency and accountability.
Excellent communication, presentation, interpersonal, and teamwork skills.
Highly motivated, self-starting, can-do attitude; out-of-the-box thinking; and willingness to take informed risks to achieve organizational goals.

Responsibilities

Lead foundry yield improvement by mitigating systematic and parametric yield detractors.
Manage foundry yield excursions and implementation of Continuous Improvement Plans.
Manage foundry safe launch.
Provide technical guidance on foundry fab-transfer projects.
During development, direct wafer-lot progress, process-skew splits, and DOE strategies.
Support device-performance analysis for mixed-signal devices.
Manage compliance with fab yield, E-test, WAT, and inline Cp/CpK metrics.
Serve as technical liaison to foundries and communicate process-health-monitor status to internal stakeholders.
Drive on-time wafer output from the fab, continuous-improvement deliverables, and resolution of critical technical escalations.