Sr Principal Digital Design Engineer

Marvell Technology•San Diego, CA

23h

About The Position

Join Marvell's Custom Compute Solutions Business Unit (CCSBU) as we establish our design presence in San Diego's thriving semiconductor ecosystem. This team will be responsible for delivering high‑quality customer silicon for advanced AI, XPU, and XPU‑Attach programs. By partnering closely with customers and internal stakeholders, the design center will enable Marvell’s most strategic and financially significant custom SoC initiatives, delivering differentiated solutions that reinforce Marvell’s position as a trusted partner for next‑generation compute platforms. This is a rare technical leadership opportunity - you'll help shape design strategy from the ground up and build a world-class team as part of our strategic expansion into Southern California. You're not joining an established local team - you're building one. You'll define the culture, establish the methodology, and shape the technical DNA of Marvell's San Diego design organization.

Requirements

Fluent in SystemVerilog RTL coding techniques.
Experience in high speed, multiple clock domain designs
Expertise in PCIe, CXL protocols
Familiar with modern SoC architectures and various interface technologies such as AXI, DDR, Ethernet, PCIe.
Experience in micro-architecture of complex custom/ASIC products involving Chip I/O, shared memory, and embedded processors
RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.
Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies.
Ability to create SVA assertions and apply formal verification concepts and tools
Ability to come up with creative and innovative solutions, and display technical leadership from within a team of engineers
Excellent verbal and written communication
Discipline and rigor in documentation
Ability to work efficiently and influentially with team members across multiple sites
Enthusiastic about exploring and applying new methods, tools, and process efficiency to ASIC design flow

Nice To Haves

Experience in designing high speed (>1 GHz)/high-performance embedded processor SOC products is a plus.
Experience in implementation/timing closure for high speed design.
Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is desirable.

Responsibilities

Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits.
Work closely with system and chip architects to design industrial quality implementations.
Participate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs.
Produce comprehensive block uArchitecture and register Specs.
Schedule detailed reviews with cross-functional teams
Evaluate and participate in improving design and verification methodologies.
Supervise or mentor other digital design engineers.