Sr. Principal Design Engineer CMOS

Northrop Grumman•Manhattan Beach, CA

4d•$142,200 - $213,400

About The Position

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. Seeking a Senior CMOS Design Engineer to lead RF and mixed-signal IC development for space payloads. This role provides technical leadership across architecture, transistor-level design, verification, and silicon validation for radiation-tolerant, high-reliability CMOS ICs. Please be aware that this position is contingent upon capturing program award(s) and obtaining and maintaining associated business and/or customer funding.

Requirements

Bachelor’s degree in Electrical Engineering (or related field) with 9+ years of relevant CMOS design experience; or Master’s degree with 7+ years of relevant CMOS design experience; or PhD with 4+ years of relevant CMOS design experience.
Demonstrated leadership in transistor-level CMOS RF and/or mixed-signal IC design through multiple full design cycles.
Deep understanding of analog/RF design principles, including stability, noise, linearity, and layout‑dependent effects.
Proficiency with SPICE-based simulation, Cadence (or similar) design environments, and advanced verification techniques.
Proven experience guiding layout, closing DRC/LVS, and managing block- and top-level integration.
Strong technical communication and experience presenting to cross-functional and leadership audiences.
U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.

Nice To Haves

IC design experience for space, radiation-tolerant, or other harsh environments (rad-hard design techniques, TID/SEE considerations).
Experience with RF front ends, data converters, synthesizers/PLLs, or mixed-signal readout ASICs for space payloads.
Hands-on leadership in lab validation and silicon debug using RF and mixed-signal measurement equipment.
Experience mentoring junior engineers and influencing technical direction at the program or product level.
Experience with heterogeneous integration approaches
Active security clearance

Responsibilities

Lead the design, simulation, and verification of RF / mixed-signal CMOS blocks and subsystems for space payload applications.
Define architectures, specifications, and performance budgets in collaboration with systems, digital, and packaging teams.
Drive pre- and post-layout analyses (PVT, Monte Carlo, noise, linearity, reliability) and close on performance, power, and area targets.
Provide technical direction to layout and junior design engineers; ensure robust layout practices for radiation and reliability.
Plan and conduct design reviews; identify risks and propose mitigation strategies.
Lead silicon bring-up, lab characterization, debug, and correlation to simulations; support development of production test strategies.
Contribute to roadmaps and technology insertion for next-generation space payload ICs.