Sr Principal ASIC Design Engineer - Terawave
About The Position
Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. We are seeking ASIC/SOC Design engineers (levels including Principal, Senior Principal) who are critical to ensuring our RFIC/ASIC designs culminate in thoroughly designed and validated cutting-edge integrated circuits that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth. This role requires a highly skilled Design and Verification Engineer with extensive experience in complex SoC design, integration, and verification. The candidate will be responsible for driving end-to-end design and verification methodologies, from writing requirements and specifications to post-silicon bring-up. Strong expertise in Verilog/System Verilog, DSP structures, modem SOCs, ARM CPU integration, and interface protocols is essential, along with the ability to optimize performance and power, support back-end teams, and ensure seamless portability across FPGA and silicon environments.
Requirements
- BS, MS in Electrical Engineering or a related technical discipline
- 15+ years of experience
- Deep working knowledge and hands-on experience in innovative verification flows
Responsibilities
- Design and Verification Verilog/System Verilog experience in designing complex SOCs
- CDC, RDC, LINT
- Write requirements, specifications and test plans
- Optimize performance while keeping power low
- Clock gating (dynamic and static)
- Multi-voltage SOC front end design
- Formal verification
- Functional coverage, definition and collection
- Module verification
- Complex subsystem verification
- Complex SoC verification
- Co-simulation with software, integration of software build tool flow with simulation
- Gate simulation
- External IP integration
- ARM CPU single and multi-core integration with bus fabric, GIC, cache, MMU, secure boot
- AXI bus complex
- High performance DMA
- NOC integration
- DDR, PCIE, Ethernet, SPI integration
- High speed serdes integration
- DSP structures (FIR, Cordic, FFT/IFFT, MAC, circular buffers, analog-digital interface)
- Modem using state of the art DSP, coding, framing (phy and MAC)
- Sequenced and time bound data movement in DSP structures (time slots, time stamps etc)
- SOC top level integration using models for analog macros
- Verification using golden reference models in Matlab, SystemC or C
- Code coverage
- Timing constraints
- Support back-end teams during DFT, LEC, floorplan, STA
- Post silicon bring up
- FPGA ASIC to/from FPGA flow
Benefits
- Medical, dental, vision, basic and supplemental life insurance
- Paid parental leave
- Short and long-term disability
- 401(k) with a company match of up to 5%
- Education Support Program
- Stock Options for all regular employees (working at least 20 hours/week)
- Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours
- Up to 14 company-paid holidays
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What This Job Offers
Job Type
Full-time
Career Level
Senior
