SPE Signal Integrity

Rambus•Johns Creek, GA

1d•Hybrid

About The Position

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr Principal Applications Engineer with DRAM and failure analysis expertise to analyze and debug complex technical issues involving DRAM, memory interface chips, DIMM, server and BIOS operation and interaction. This individual will support international customers of Rambus DDR4 and DDR5 memory interface chips in South Korea and Asia. You will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work.

Requirements

Familiar with DDR4/DDR5 DIMM memory operation in Intel, AMD, and/or OEM servers.
Good understanding of signal integrity issues at clock rates of 3 GHz and above.
Experience with power management and I2C/I3C serial interfaces.
Extensive experience with probing, using high speed oscilloscopes and other lab equipment.
History of using fundamental root cause techniques (fishbone, design of experiments, etc.) to solve complex problems.
Ability to use scripting languages such as Perl, Tcl or Python to analyze data log text files and automate system and bench testing.
Ability to travel to customer sites as needed, including international travel.
Excellent verbal and written communications skills in English and Korean.
BS degree or higher in Electrical Engineering or related field.
12+ years of experience in hardware design, validation, and/or applications engineering.

Nice To Haves

Good understanding of ATE tester operation is a strong plus.
Past experience reading and modifying MRC BIOS code and utilizing server platform debug tools (either Intel or AMD) is strongly desired.

Responsibilities

Analyze and debug complex technical issues involving server memory and manage customer issues to a satisfactory conclusion.
Support technical qualification of new chip designs to secure customer design wins.
Assist with validation and debug of new memory interface chips for DDR5 servers.
Collect and analyze signal integrity data at the system level.
Conduct failure analysis and prepare failure analysis and 8D reports.
Gather customer technical feedback and communicate to Marketing and Engineering teams.
Present technical updates to customers and company management in writing and verbally via quality presentations.
Prepare technical documentation such as datasheets, user guides and application notes.