Senior Signal/Power Integrity Engineer

Astera Labs•San Jose, CA

2d•$147,000 - $195,000

About The Position

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. At Astera Labs, we seek motivated Senior SI/PI and System Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. You will also formulate a comprehensive system validation plan and design experiments to root cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness.

Requirements

Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred.
2+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and Networking applications.
2+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.
Cross-functional design mentality.
Self-starting, professional, and hands-on work ethic that can execute in a dynamic environment.
Proven track record solving problems independently.
Entrepreneurial, open-minded behavior, and can-do attitude.
Authorized to work in the US and start immediately.
Familiar with SI and PI design challenges for high-speed boards and interconnects
2D and 3D simulation experience with Cadence/Mentor/Ansys/ADS/etc. toolsets
High-speed SERDES measurement, channel simulation, and equalization
Expertise in PAM4 and NRZ signaling, COM, BER, jitter analysis
Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc.
Familiarity with PCIe5/6 and CXL specs, especially Electrical Compliance sections
Proficiency in using high-speed lab equipment such as BERT, Oscilloscope, and VNA
Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment.