Sr PD Engineer
About The Position
Qualcomm Atheros, Inc. (QCA) is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team, the role will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs. Qualcomm’s Connectivity SoC organization is seeking candidates for physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies. Tasks also involve the tiles level development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals. This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.
Requirements
- 2+ years industry experience in Tiles level or sub-system level or SoC top level physical design successful tapeout experience.
- Floorplanning of macro cells.
- Place & Route (PNR) tool experience on Cadence Innovus and/or Synopsys Fusion Compiler.
- Timing closure (STA) experience in Synopsys PTSI.
- Function ECO implementation.
- Formal verification (FV) experience.
- Power domain analysis (IR Drop/PDN) experience.
- Physical verification (PV) experience.
- Deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell.
Responsibilities
- Innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.
- Tiles level development and enablement of low power implementation methods.
- Customized P&R to achieve area reduction, performance, and power goals.
- Experience of functional and test (DFT) mode constraints for place and route.
- Floorplanning, power planning.
- IR drop analysis.
- Routing, timing optimization and closure.
- Implementing timing fixes and functional ECOs.
- Debugging and fixing physical violations and formal verification.
- Design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Senior
