Sr. IP Logic Design Engineer

Intel • Us, CA

1d • Hybrid

About The Position

Key Responsibilities: Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs. Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks. Develop RTL code for core components of the memory fabric, ensuring optimal performance, area, and power trade-offs. Work closely with verification teams to create test plans and debug issues arising during pre-silicon validation. Collaborate with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems. Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases. Mentor junior engineers and contribute to technical reviews and design documentation. Stay updated with emerging technologies and trends in memory subsystems, coherency protocols, and AI/ML hardware. Qualifications: Minimum Requirements: Education: MS/PhD in Electrical Engineering, Computer Engineering, or related field. Experience: 10+ years in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding. Technical Skills: Expertise in memory coherency protocols (e.g., MESI, MOESI, CXL, CCIX, CHI). Strong knowledge of interconnect technologies (e.g., AMBA, PCIe, NoC architectures). Proven RTL coding experience in Verilog or SystemVerilog. Proficiency in simulation tools for performance modeling and analysis. Familiarity with physical design implications of memory fabric architectures (timing, power, area). Experience with EDA tools for synthesis, linting, and static timing analysis. Preferred Skills: Hands-on experience with high-bandwidth memory (HBM), DDR, or other advanced memory technologies. Background in AI/ML accelerator or data center SoC design. Knowledge of scripting languages like Python or TCL for workflow automation. Experience with software-hardware co-design for end-to-end system optimization. Soft Skills: Strong problem-solving and debugging skills. Excellent communication and collaboration abilities. Ability to manage and prioritize multiple tasks effectively.

Requirements

• MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• 10+ years in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding.
• Expertise in memory coherency protocols (e.g., MESI, MOESI, CXL, CCIX, CHI).
• Strong knowledge of interconnect technologies (e.g., AMBA, PCIe, NoC architectures).
• Proven RTL coding experience in Verilog or SystemVerilog.
• Proficiency in simulation tools for performance modeling and analysis.
• Familiarity with physical design implications of memory fabric architectures (timing, power, area).
• Experience with EDA tools for synthesis, linting, and static timing analysis.
• Strong problem-solving and debugging skills.
• Excellent communication and collaboration abilities.
• Ability to manage and prioritize multiple tasks effectively.

Nice To Haves

• Hands-on experience with high-bandwidth memory (HBM), DDR, or other advanced memory technologies.
• Background in AI/ML accelerator or data center SoC design.
• Knowledge of scripting languages like Python or TCL for workflow automation.
• Experience with software-hardware co-design for end-to-end system optimization.

Responsibilities

• Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.
• Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks.
• Develop RTL code for core components of the memory fabric, ensuring optimal performance, area, and power trade-offs.
• Work closely with verification teams to create test plans and debug issues arising during pre-silicon validation.
• Collaborate with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems.
• Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases.
• Mentor junior engineers and contribute to technical reviews and design documentation.
• Stay updated with emerging technologies and trends in memory subsystems, coherency protocols, and AI/ML hardware.

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel .

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees