Sr. Hardware Engineer (EDVT & PHY Qual)

Cisco•San Jose, CA

1d•$154,900 - $225,300

About The Position

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. As a Senior Hardware Validation Engineer, you will lead the electrical design validation and physical layer (PHY) qualification for our next-generation enterprise and industrial switches. You will be responsible for ensuring our hardware meets the highest quality, performance, and industry standards. As a Sr. Hardware Engineer, you will drive product excellence by designing and executing comprehensive, end-to-end test architectures across complex board components and PHY systems. Leveraging test automation, scripting, and cross-functional collaboration, you will debug root-cause issues and ensure seamless compliance with industry standards for successful mass production releases. Beyond technical execution, you will act as a key technical leader—owning critical projects, mentoring junior engineers, and establishing standard test frameworks that scale product quality across the organization.

Requirements

Bachelor’s degree in Electrical or Computer Engineering (7+ years of experience) or MSEE/CE (5+ years of experience).
Prior experience in the field of networking hardware validation/testing.
Prior hands-on experience with electrical and optical test equipment (Oscilloscopes, Power meters, Signal generators, VNA (Vector Network Analyzers), and Thermal chambers).
Prior experience with L2/L3 routing and switching, OSI Model, and LAN/WAN topologies.
Prior experience with Python for test automation.

Nice To Haves

Prior experience with high-speed interfaces, including 10G/25G/100G/400G network interfaces.
Prior experience with PHY/Signal Integrity for high-pass/low-pass filters, and IEEE 802.3 signal compliance testing.
Prior experience with Power/Bus architecture, including prior knowledge of Power over Ethernet (PoE) testing, CPU, clocking, and bus architectures (PCIe, USB, I2C).
Prior experience with traffic generators such as Ixia or Spirent.
Prior experience with EMI/EMC testing and regulatory compliance.

Responsibilities

Lead the electrical design validation and physical layer (PHY) qualification for next-generation enterprise and industrial switches.
Ensure hardware meets the highest quality, performance, and industry standards.
Design and execute comprehensive, end-to-end test architectures across complex board components and PHY systems.
Leverage test automation and scripting to debug root-cause issues.
Ensure seamless compliance with industry standards for successful mass production releases.
Act as a key technical leader, owning critical projects.
Mentor junior engineers.
Establish standard test frameworks that scale product quality across the organization.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
grants of Cisco restricted stock units
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year (non-exempt employees)
flexible vacation time off program (exempt employees)
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)