Sr. Hardware Engineer (Teradyne, Oregon)

Teradyne•Tualatin, OR

22h•Onsite

About The Position

The Senior Hardware Engineer in the hardware group is responsible for designing, developing, and validating high‑current, high‑power sourcing and switching hardware used in semiconductor automated test equipment. This role focuses on power delivery architecture, fast transient response, load regulation, protection systems, thermal management, and system‑level integration to support advanced SoCs, FPGAs, high‑power devices, and complex test conditions. The engineer owns power‑delivery modules from concept through production release and collaborates across hardware, firmware, mechanical, and test engineering teams.

Requirements

8- 10+ years of experience in power electronics, high‑current power delivery, or instrumentation hardware design.
Strong expertise in switching power supplies, multiphase regulators, linear regulators, and power‑stage design.
Experience with power integrity, transient analysis, and compensation/stability design.
Proficiency with SPICE simulation, PDN modeling tools, and PCB design tools.
Hands‑on experience with power measurement equipment and high‑current test setups.
Strong analytical and debugging skills.
Bachelor’s or Master’s degree in Electrical Engineering or related field.

Nice To Haves

Experience designing power‑delivery modules for ATE instrumentation.
Knowledge of dynamic voltage scaling, digital power control, and telemetry systems.
Familiarity with high‑current connectors, cabling, and low‑impedance mechanical design.
Understanding of thermal modeling, heatsink design, and system‑level thermal constraints.

Responsibilities

Architect and design high‑current power delivery modules (from mA to 100+ A) for ATE systems.
Develop fast‑response voltage/current sourcing circuits optimized for dynamic load conditions, droop control, and transient performance.
Implement advanced power‑stage topologies (buck, multiphase, linear, hybrid) tailored for semiconductor test environments.
Design for wide operating ranges, including high‑voltage rails, low‑voltage/high‑current rails, and dynamic voltage scaling.
Optimize power integrity across the full PDN (instrumentation → cabling → loadboard → DUT).
Model and mitigate droop, overshoot, ringing, and ground bounce under fast load steps.
Perform simulation and analysis of loop stability, compensation networks, and transient response.
Ensure compliance with DUT power‑up sequencing, ramp rates, and timing constraints.
Design robust protection systems including OCP, OVP, OTP, short‑circuit protection, and fault‑isolation mechanisms.
Implement fast fault‑response circuits to protect sensitive DUTs and ATE hardware.
Conduct reliability analysis, derating studies, and thermal modeling for long‑term stability.
Support HALT/HASS, stress testing, and failure‑mode investigations.
Develop efficient high‑current solutions for routing power to multiple DUT pins or sites.
Engineer low‑impedance, low‑loss paths for high‑current delivery with attention to thermal and mechanical constraints.
Collaborate with mechanical teams on heatsinking, airflow, and thermal interface design.
Lead bring‑up of new power‑delivery modules, performing root‑cause analysis of analog, digital, and mixed‑signal issues.
Execute characterization plans for load regulation, transient response, efficiency, thermal behavior, and fault handling.
Use advanced lab equipment (power analyzers, high‑bandwidth scopes, current probes, electronic loads) to validate performance.
Ensure power‑delivery modules meet ATE system‑level requirements for timing, triggering, synchronization, and software control.
Collaborate with firmware teams on control loops, telemetry, calibration, and fault‑reporting algorithms.
Create and use ATE test programs to validate instrument and system level designs.
Support integration with loadboards, probecards, and DUT power‑delivery networks.
Work with product engineering, test engineering, and silicon teams to define power‑delivery requirements for new devices.
Provide technical mentorship and contribute to power‑delivery design standards and best practices.