Sr. FPGA Engineer

Xona Space SystemsBurlingame, CA

About The Position

Xona is the navigational intelligence company bringing real-time, centimeter-level certainty to any device, anywhere on Earth. With Pulsar – the world’s most advanced PNT satellite infrastructure in Low Earth Orbit – Xona will offer a future-proof, backwards-compatible global positioning system optimized for absolute precision, superior power, and robust protection. We’re seeking a Senior FPGA Engineer to lead the architectural specification and design of next-generation LEO PNT satellite systems. You will own the FPGA signal-processing pipeline from concept through flight-ready hardware, making critical trade-offs between mathematical idealization and physical hardware constraints.

Requirements

  • PhD or MS/BS in EE/CE or related field, 7+ years of FPGA and DSP implementation experience.
  • Demonstrated ownership of complex FPGA signal-processing systems from architecture to hardware validation.
  • Deep expertise in fixed-point DSP implementation, pipelining, and resource optimization.
  • Strong experience with high-speed interfaces and complex FPGA subsystems.
  • Expert proficiency with FPGA toolchains, static timing analysis, and on-chip debugging.

Nice To Haves

  • Experience with satellite communications, esp. with GNSS receivers and in spread-spectrum systems.
  • Familiarity with processing of satellite-related measurements (code/carrier/Doppler/CN0, PRs, DRs).
  • Experience supporting HIL and over-the-air validation environments.

Responsibilities

  • Define and specify hardware architecture for high-dynamic acquisition, tracking, data decoding, and measurement processing pipelines.
  • Lead fixed-point design, resource budgeting, and pipeline optimization to achieve performance and latency targets.
  • Establish RTL best practices and guide junior engineers through complex design cycles and hardware validation phases.
  • Define and optimize HW/SW partitioning in collaboration with SW teams; ensure efficient SW interfaces, seamless integration, robust system-level testing, and preservation of performance margins.
  • Drive timing closure, power optimization, and system-level performance verification; resolve complex cross-domain issues.
  • Evaluate and integrate third-party IP cores, define acceptance criteria and compliance testing.
  • Establish robust verification frameworks, including simulation, emulation, and hardware validation.
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