Sr FPGA Design Engineer (NetSec)

Palo Alto Networks•Office - USA - CA - Headquarters, CA

2d•$156,400 - $253,000•Onsite

About The Position

Join Palo Alto Networks’ FPGA engineering team to develop high-performance digital logic, CPLD/CFPGA modules, and hardware acceleration platforms for next-generation firewalls. The engineer owns FPGA design from architecture and specification through RTL development, timing closure, synthesis, and laboratory bring-up, working closely with software, hardware, and verification teams. The role involves developing designs for AMD/Xilinx and Altera/Intel FPGA architectures, validating ASIC designs on FPGA platforms, integrating complex IP blocks, and optimizing timing, power, and resource utilization. The engineer will also pilot AI-driven design or verification workflows to reduce schedule risk. Palo Alto Networks says most teams work from the office full time, with flexibility when needed.

Requirements

Bachelor’s degree in EE, CE, or CS.
At least 10 years of front-end ASIC design ownership and a record of shipping at least two chips to mass production.
Expertise in SystemVerilog and Verilog RTL development for FPGA and CPLD architectures.
Proven experience with FPGA synthesis, placement, routing, and static timing analysis closure across multi-clock domains.
Scripting proficiency in Python, C/C++, Perl, bash, or tcsh.
Experience integrating and configuring high-speed IP cores such as PCIe Gen4/5/6, QDMA, Ethernet MAC/PHY, and memory controllers.
Experience with FPGA rapid prototyping, in-system logic debugging using tools such as ILA or SignalTap, and lab bring-up.
Ability to optimize FPGA resource utilization, including LUTs, FFs, BRAM/URAM, and DSP blocks, and apply timing-closure strategies.
Ability to analyze timing, power, and area reports and drive corrective actions.
Proficiency or active experience integrating modern AI tools into hardware design, scripting, or verification workflows.
Excellent leadership, collaboration, and written and verbal communication skills.

Nice To Haves

MSEE or equivalent military experience.
Experience with ASIC-to-FPGA prototyping flows and emulation environments.
Hands-on experience with high-density FPGA platforms such as AMD UltraScale+ or Altera Agilex/Stratix.
Experience applying formal verification techniques, such as VC Formal, to FPGA module verification.
Networking protocol experience, including Ethernet, eDSA, IPsec, or packet processing, and experience designing CPLD/CFPGA board-management logic.

Responsibilities

Write comprehensive micro-architecture and functional specifications for FPGA, CFPGA, and CPLD designs.
Develop SystemVerilog and Verilog RTL for advanced FPGA architectures while meeting timing, power, and area targets.
Synthesize and implement designs using Vivado, Quartus, and Synopsys tools, closing timing across multiple clock domains and optimizing resource use.
Prototype and validate ASIC designs on FPGA platforms, including laboratory bring-up, in-system debugging, and hardware validation.
Collaborate with software and platform teams to define interfaces, review memory map structures, and integrate IP blocks such as PCIe, Ethernet, QDMA, and DDR/LPDDR.
Pilot AI-driven design or verification workflows to reduce schedule risk.